MPC561MZP56 Freescale, MPC561MZP56 Datasheet - Page 1002

MPC561MZP56

Manufacturer Part Number
MPC561MZP56
Description
Manufacturer
Freescale
Datasheet

Specifications of MPC561MZP56

Cpu Family
MPC56x
Device Core
PowerPC
Device Core Size
32b
Frequency (max)
56MHz
Interface Type
QSPI/SCI/SPI/UART
Total Internal Ram Size
32KB
# I/os (max)
56
Number Of Timers - General Purpose
22
Operating Supply Voltage (typ)
2.6/5V
Operating Supply Voltage (max)
2.7/5.25V
Operating Supply Voltage (min)
2.5/4.75V
On-chip Adc
2(32-chx10-bit)
Instruction Set Architecture
RISC
Operating Temp Range
-40C to 125C
Operating Temperature Classification
Automotive
Mounting
Surface Mount
Pin Count
388
Package Type
BGA
Program Memory Type
ROMLess
Program Memory Size
Not Required
Lead Free Status / RoHS Status
Not Compliant

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READI Module
24.7.6
The READI reset configuration information is received via EVTI and MDI0 to enable or disable the
READI module and select the port size. EVTI and MDI0 are sampled synchronously at the negation of
RSTI. Reset configuration information must be valid on EVTI and MDI0 at least four clocks prior to the
negation of RSTI.
If EVTI is sampled asserted at negation of RSTI, the READI module will be enabled. This is illustrated in
Figure
READI control and status information will be reset and the auxiliary output port will be three-stated, when
RSTI is asserted. System reset will not reset the READI control and status information and not three-state
the auxiliary output port.
Port size configuration is selected via the value of MDI0 at the negation of RSTI.
the READI reset configuration options.
RSTI has a pull-down resistor in the pads. If the auxiliary port is not connected to a tool, READI module
will be in reset state and not drive the auxiliary output port.
24-34
System
Clock
RSTI
EVTI
24-15.
READI Reset Configuration
Reset configuration information must be valid on EVTI
at least 4 system clocks prior to RSTI negation.
EVTI
1
0
0
Table 24-25. READI Reset Configuration Options
MDI [0]
MPC561/MPC563 Reference Manual, Rev. 1.2
X
1
0
Figure 24-15. READI Module Enabled
Module Enabled, Default Full Port Configuration
Module Enabled, Reduced Port Configuration
Module Disabled. All outputs three-stated.
EVTI is sampled at the negation of RSTI. Because EVTI is
asserted, the READI module is enabled.
Configuration
2 MDI, 8 MDO
1 MDI, 2 MDO
Table 24-25
Freescale Semiconductor
describes

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