MPC561MZP56 Freescale, MPC561MZP56 Datasheet - Page 728
MPC561MZP56
Manufacturer Part Number
MPC561MZP56
Description
Manufacturer
Freescale
Datasheet
1.MPC561MZP56.pdf
(1420 pages)
Specifications of MPC561MZP56
Cpu Family
MPC56x
Device Core
PowerPC
Device Core Size
32b
Frequency (max)
56MHz
Interface Type
QSPI/SCI/SPI/UART
Total Internal Ram Size
32KB
# I/os (max)
56
Number Of Timers - General Purpose
22
Operating Supply Voltage (typ)
2.6/5V
Operating Supply Voltage (max)
2.7/5.25V
Operating Supply Voltage (min)
2.5/4.75V
On-chip Adc
2(32-chx10-bit)
Instruction Set Architecture
RISC
Operating Temp Range
-40C to 125C
Operating Temperature Classification
Automotive
Mounting
Surface Mount
Pin Count
388
Package Type
BGA
Program Memory Type
ROMLess
Program Memory Size
Not Required
Lead Free Status / RoHS Status
Not Compliant
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Company:
Part Number:
MPC561MZP56
Manufacturer:
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CAN 2.0B Controller Module
16-34
10:11
Bits
0:1
12
2
3
4
5
6
7
8
9
STUFFERR
FORMERR
RXWARN
CRCERR
TXWARN
ACKERR
BITERR
TX/RX
Name
IDLE
FCS
—
Transmit bit error. The BITERR[1:0] field is used to indicate when a transmit bit error occurs.
Refer to
NOTE: The transmit bit error field is not modified during the arbitration field or the ACK slot
bit time of a message, or by a transmitter that detects dominant bits while sending a passive
error frame.
Acknowledge error. The ACKERR bit indicates whether an acknowledgment has been
correctly received for a transmitted message.
0 No ACK error was detected since the last read of this register
1 An ACK error was detected since the last read of this register
Cyclic redundancy check error. The CRCERR bit indicates whether or not the CRC of the
last transmitted or received message was valid.
0 No CRC error was detected since the last read of this register
1 A CRC error was detected since the last read of this register
Message format error. The FORMERR bit indicates whether or not the message format of
the last transmitted or received message was correct.
0 No format error was detected since the last read of this register
1 A format error was detected since the last read of this register
Bit stuff error. The STUFFERR bit indicates whether or not the bit stuffing that occurred in
the last transmitted or received message was correct.
0 No bit stuffing error was detected since the last read of this register
1 A bit stuffing error was detected since the last read of this register
Transmit error status flag. The TXWARN status flag reflects the status of the TouCAN
transmit error counter.
0 Transmit error counter < 96
1 Transmit error counter ≥ 96
Receiver error status flag. The RXWARN status flag reflects the status of the TouCAN
receive error counter.
0 Receive error counter < 96
1 Receive error counter ≥ 96
Idle status. The IDLE bit indicates when there is activity on the CAN bus.
0 The CAN bus is not idle
1 The CAN bus is idle
Transmit/receive status. The TX/RX bit indicates when the TouCAN module is transmitting or
receiving a message. TX/RX has no meaning when IDLE = 1.
0 The TouCAN is receiving a message if IDLE = 0
1 The TouCAN is transmitting a message if IDLE = 0
Fault confinement state. The FCS[1:0] field describes the state of the TouCAN. Refer to
Table
If the SOFTRST bit in CANMCR is asserted while the TouCAN is in the bus off state, the error
and status register is reset, including FCS[1:0]. However, as soon as the TouCAN exits reset,
FCS[1:0] bits will again reflect the bus off state. Refer to
more information on entry into and exit from the various fault confinement states.
Reserved
16-25.
Table
MPC561/MPC563 Reference Manual, Rev. 1.2
Table 16-23. ESTAT Bit Descriptions
16-24.
Description
Section 16.3.4, “Error
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