MPC561MZP56 Freescale, MPC561MZP56 Datasheet - Page 246

• Manufacturer Part Number: MPC561MZP56
• Manufacturer: Freescale

Specifications of MPC561MZP56

• Cpu Family: MPC56x
• Device Core: PowerPC
• Device Core Size: 32b
• Frequency (max): 56MHz
• Interface Type: QSPI/SCI/SPI/UART
• Total Internal Ram Size: 32KB
• # I/os (max): 56
• Number Of Timers - General Purpose: 22
• Operating Supply Voltage (typ): 2.6/5V
• Operating Supply Voltage (max): 2.7/5.25V
• Operating Supply Voltage (min): 2.5/4.75V
• On-chip Adc: 2(32-chx10-bit)
• Instruction Set Architecture: RISC
• Operating Temp Range: -40C to 125C
• Operating Temperature Classification: Automotive
• Mounting: Surface Mount
• Pin Count: 388
• Package Type: BGA
• Program Memory Type: ROMLess
• Program Memory Size: Not Required
• Lead Free Status / RoHS Status: Not Compliant

System Configuration and Protection
occupying the external bus. Internal bus arbitration is selected by clearing SIUMCR[EARB] (see
Section 6.2.2.1.1, “SIU Module Configuration Register
6.1.2.2
During an external master access, the USIU compares the external address with the internal address block
to determine if MPC561/MPC563 operation is required. Since only 24 of the 32 internal address bits are
available on the external bus, the USIU assigns zeros to the most significant address bits (ADDR[0:7]).
The address compare sequence can be summarized as follows:
When trying to fetch an MPC561/MPC563 special register from an external master, the address might be
aliased to one of the external devices on the external bus. If this device is selected by the
MPC561/MPC563 internal memory controller, this aliasing does not occur since the chip select is
disabled. If the device has its own address decoding or is being selected by external logic, this case is
resolved.
6.1.3
The USIU provides 64 general-purpose I/O (SGPIO) pins (See
multiplexed with the address and data pins. In single-chip mode, where communicating with external
devices is not required, all 64 SGPIO pins can be used. In multiple-chip mode, only eight SGPIO pins are
available. Another configuration allows the use of the address bus for instruction show cycles while the
data bus is dedicated to SGPIO functionality. The functionality of these pins is assigned by the single-chip
(SC) bit in the SIUMCR. (See
SGPIO pins are grouped as follows:
Table 6-2
described in
6-6
•
•
•
Normal external access. If EMCR[CONT] is cleared, the address is compared to the internal
address map. Refer to
— MPC561/MPC563 special register external access. If EMCR[CONT] is set by the previous
— Memory controller external access. If the first two comparisons do not match, the internal
Six groups of eight pins each, whose direction is set uniformly for the whole group
16 single pins whose direction is set separately for each pin
describes the SGPIO signals, and all available configurations. The SGPIO registers are
external master access, the address is compared to the MPC561/MPC563 special address
range. See
memory controller determines whether the address matches an address assigned to one of the
regions. If it finds a match, the memory controller generates the appropriate chip select and
attribute accordingly
USIU General-Purpose I/O
Section 6.2.2.5, “General-Purpose I/O
Address Decoding for External Accesses
This section does not address slave accesses to internal resources. For
internal resources, the accesses compare against ADDR[8:9] = ISB[1:2].
ISB0 must be cleared.
Section 5.1.1, “USIU Special-Purpose
Section 6.2.2.1.3, “External Master Control Register
Section 6.2.2.1.1, “SIU Module Configuration Register
MPC561/MPC563 Reference Manual, Rev. 1.2
NOTE
Registers.”
(SIUMCR)”).
Registers,” for a list of the SPRs in the USIU.
Table
6-2). The SGPIO pins are
(EMCR)”.
Freescale Semiconductor
(SIUMCR).”)