MPC561MZP56 Freescale, MPC561MZP56 Datasheet - Page 762

• Manufacturer Part Number: MPC561MZP56
• Manufacturer: Freescale

Specifications of MPC561MZP56

• Cpu Family: MPC56x
• Device Core: PowerPC
• Device Core Size: 32b
• Frequency (max): 56MHz
• Interface Type: QSPI/SCI/SPI/UART
• Total Internal Ram Size: 32KB
• # I/os (max): 56
• Number Of Timers - General Purpose: 22
• Operating Supply Voltage (typ): 2.6/5V
• Operating Supply Voltage (max): 2.7/5.25V
• Operating Supply Voltage (min): 2.5/4.75V
• On-chip Adc: 2(32-chx10-bit)
• Instruction Set Architecture: RISC
• Operating Temp Range: -40C to 125C
• Operating Temperature Classification: Automotive
• Mounting: Surface Mount
• Pin Count: 388
• Package Type: BGA
• Program Memory Type: ROMLess
• Program Memory Size: Not Required
• Lead Free Status / RoHS Status: Not Compliant

Modular Input/Output Subsystem (MIOS14)
mode selection. Data registers A and B are accessible at consecutive addresses. Writing to data register B
stores the same value in registers B1 and B2.
17.9.3.2
IPWM mode is selected by setting MODE[0:3] to 0b0001.
This mode allows the width of a positive or negative pulse to be determined by capturing the leading edge
of the pulse on channel B and the trailing edge of the pulse on channel A; successive captures are done on
consecutive edges of opposite polarity. The edge sensitivity is selected by the EDPOL bit in the
MDASMSCR register.
This mode also allows the software to determine the logic level on the input signal at any time by reading
the PIN bit in the MDASMSCR register.
The channel A input capture function remains disabled until the first leading edge triggers the first input
capture on channel B (refer to
16-bit counter bus selected by the BSL[1:0] bits is latched in the 16-bit data register B1; the FLAG line is
not activated. When the next trailing edge is detected, the count value of the 16-bit counter bus is latched
into the 16-bit data register A and, at the same time, the FLAG line is activated and the contents of register
B1 are transferred to register B2.
Reading data register B returns the value in register B2. If subsequent input capture events occur while the
FLAG bit is set in the corresponding MIRSM, data registers A and B will be updated with the latest
captured values and the FLAG line will remain active.
If a 32-bit coherent operation is in progress when the trailing edge is detected, the transfer from B1 to B2
is deferred until the coherent operation is completed. Operation of the MDASM then continues on
channels B and A as previously described.
The input pulse width is calculated by subtracting the value in data register B from the value in data register
A.
Figure 17-16
17-30
Input Pulse Width Measurement (IPWM) Mode
provides an example of how the MDASM can be used for input pulse width measurement.
When changing modes, it is imperative to go through the DIS mode. Failure
to do this could lead to invalid and unexpected output compare or input
capture results, and to flags being set incorrectly.
Figure
MPC561/MPC563 Reference Manual, Rev. 1.2
17-16). When this leading edge is detected, the count value of the
WARNING
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