HD64F3026X25 Renesas Electronics America, HD64F3026X25 Datasheet - Page 93
![MCU 3V 256K 100-TQFP](/photos/28/61/286123/100-tqfp__100-vqfp_sml.jpg)
HD64F3026X25
Manufacturer Part Number
HD64F3026X25
Description
MCU 3V 256K 100-TQFP
Manufacturer
Renesas Electronics America
Series
H8® H8/300Hr
Datasheet
1.DF3026XBL25V.pdf
(843 pages)
Specifications of HD64F3026X25
Core Processor
H8/300H
Core Size
16-Bit
Speed
25MHz
Connectivity
SCI, SmartCard
Peripherals
PWM, WDT
Number Of I /o
70
Program Memory Size
256KB (256K x 8)
Program Memory Type
FLASH
Ram Size
8K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Data Converters
A/D 8x10b; D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-20°C ~ 75°C
Package / Case
100-TQFP, 100-VQFP
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
HD64F3026X25
Manufacturer:
Renesas Electronics America
Quantity:
10 000
- Current page: 93 of 843
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2.8.6
When the
bit in the condition code register is set to 1 by a reset. All interrupts are masked in the reset state.
Reset exception handling starts when the
The reset state can also be entered by a watchdog timer overflow. For details see section 11,
Watchdog Timer.
2.8.7
In the power-down state the CPU stops operating to conserve power. There are three modes: sleep
mode, software standby mode, and hardware standby mode.
Sleep Mode: A transition to sleep mode is made if the SLEEP instruction is executed while the
SSBY bit is cleared to 0 in the system control register (SYSCR). CPU operations stop
immediately after execution of the SLEEP instruction, but the contents of CPU registers are
retained.
Software Standby Mode: A transition to software standby mode is made if the SLEEP
instruction is executed while the SSBY bit is set to 1 in SYSCR. The CPU and clock halt and all
on-chip supporting modules stop operating. The on-chip supporting modules are reset, but as long
as a specified voltage is supplied the contents of CPU registers and on-chip RAM are retained.
The I/O ports also remain in their existing states.
Hardware Standby Mode: A transition to hardware standby mode is made when the
goes low. As in software standby mode, the CPU and all clocks halt and the on-chip supporting
modules are reset, but as long as a specified voltage is supplied, on-chip RAM contents are
retained.
For further information see section 20, Power-Down State.
2.9
2.9.1
The H8/300H CPU operates according to the system clock (ø). The interval from one rise of the
system clock to the next rise is referred to as a “state.” A memory cycle or bus cycle consists of
two or three states. The CPU uses different methods to access on-chip memory, the on-chip
supporting modules, and the external address space. Access to the external address space can be
controlled by the bus controller.
Reset State
Power-Down State
Basic Operational Timing
Overview
R E S
input goes low all current processing stops and the CPU enters the reset state. The I
R E S
signal changes from low to high.
Rev. 2.00 Sep 20, 2005 page 53 of 800
REJ09B0260-0200
Section 2 CPU
S T B Y
input
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