HD64F3026X25 Renesas Electronics America, HD64F3026X25 Datasheet - Page 28

• Manufacturer Part Number: HD64F3026X25
• Description: MCU 3V 256K 100-TQFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8/300Hr

Specifications of HD64F3026X25

• Core Processor: H8/300H
• Core Size: 16-Bit
• Speed: 25MHz
• Connectivity: SCI, SmartCard
• Peripherals: PWM, WDT
• Number Of I /o: 70
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 100-TQFP, 100-VQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -

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Section 9 8-Bit Timers
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Rev. 2.00 Sep 20, 2005 page xxvi of xxxviii
Setup Procedure for Waveform Output by Compare Match (Example) .............. 242
0 and 1 Output (TOA = 1, TOB = 0) ................................................................... 243
Toggle Output (TOA = 1, TOB = 0).................................................................... 243
Output Compare Output Timing.......................................................................... 244
Setup Procedure for Input Capture (Example)..................................................... 245
Input Capture (Example) ..................................................................................... 245
Input Capture Signal Timing ............................................................................... 246
Setup Procedure for Synchronization (Example)................................................. 247
Synchronization (Example) ................................................................................. 248
Setup Procedure for PWM Mode (Example)....................................................... 249
PWM Mode (Example 1)..................................................................................... 250
PWM Mode (Example 2)..................................................................................... 251
Setup Procedure for Phase Counting Mode (Example) ....................................... 252
Operation in Phase Counting Mode (Example) ................................................... 253
Phase Difference, Overlap, and Pulse Width in Phase Counting Mode............... 253
Timing for Setting 16-Bit Timer Output Level by Writing to TOLR .................. 254
Timing of Setting of IMFA and IMFB by Compare Match................................. 255
Timing of Setting of IMFA and IMFB by Input Capture .................................... 256
Timing of Setting of OVF.................................................................................... 257
Timing of Clearing of Status Flags...................................................................... 257
Contention between 16TCNT Write and Clear.................................................... 259
Contention between 16TCNT Word Write and Increment .................................. 260
Contention between 16TCNT Byte Write and Increment.................................... 261
Contention between General Register Write and Compare Match ...................... 262
Contention between 16TCNT Write and Overflow............................................. 263
Contention between General Register Read and Input Capture........................... 264
Contention between Counter Clearing by Input Capture and Counter Increment 265
Contention between General Register Write and Input Capture.......................... 266
Block Diagram of 8-Bit Timer Unit (Two Channels: Group 0)........................... 273
8TCNT Access Operation (CPU Writes to 8TCNT, Word) ................................ 287
8TCNT Access Operation (CPU Reads 8TCNT, Word) ..................................... 287
8TCNT0 Access Operation (CPU Writes to 8TCNT0, Upper Byte)................... 288
8TCNT1 Access Operation (CPU Writes to 8TCNT1, Lower Byte)................... 288
8TCNT0 Access Operation (CPU Reads 8TCNT0, Upper Byte)........................ 288
8TCNT1 Access Operation (CPU Reads 8TCNT1, Lower Byte) ....................... 288
Count Timing for Internal Clock Input................................................................ 289
Count Timing for External Clock Input (Both-Edge Detection).......................... 290
Timing of Timer Output ...................................................................................... 290
Timing of Clear by Compare Match.................................................................... 291