HD64F3026X25 Renesas Electronics America, HD64F3026X25 Datasheet - Page 523

• Manufacturer Part Number: HD64F3026X25
• Description: MCU 3V 256K 100-TQFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8/300Hr

Specifications of HD64F3026X25

• Core Processor: H8/300H
• Core Size: 16-Bit
• Speed: 25MHz
• Connectivity: SCI, SmartCard
• Peripherals: PWM, WDT
• Number Of I /o: 70
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 100-TQFP, 100-VQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -

Bit 7—Flash Memory Error (FLER): Indicates that an error has occurred during an operation on
flash memory (programming or erasing). When FLER is set to 1, flash memory goes to the error-
protection state.
Bit 7
FLER
0
1
Bits 6 to 0—Reserved: These bits are always read as 0.
17.3.3
EBR1 is an 8-bit register that specifies the flash memory erase area block by block. EBR1 is
initialized to H'00 by a reset, in hardware standby mode and software standby mode, when a low
level is input to the FWE pin, and when a high level is input to the FWE pin and the SWE bit in
FLMCR1 is not set. When a bit in EBR1 is set to 1, the corresponding block can be erased. Other
blocks are erase-protected. Only one bit can be set in EBR1 and EBR2 together; do not set two or
Bit
Initial value
Read/Write
Erase Block Register 1 (EBR1)
Description
Flash memory is operating normally
Flash memory program/erase protection (error protection) is disabled
[Clearing condition]
Reset (
An error occurred during flash memory programming/erasing
Flash memory program/erase protection (error protection) is enabled
[Setting conditions]
When flash memory is read during programming/erasing (including a vector read
or instruction fetch, but excluding a read of the RAM area overlapping flash
memory space)
Immediately after the start of exception handling during programming/erasing
(excluding reset, illegal instruction, trap instruction, and division-by-zero exception
handling)
When a SLEEP instruction (including software standby) is executed during
programming/erasing
When the bus is released during programming/erasing
R/W
EB7
7
0
R E S
pin or WDT reset) or hardware standby mode
R/W
EB6
6
0
R/W
EB5
5
0
Section 17 Flash Memory [H8/3026F-ZTAT Version]
R/W
EB4
4
0
Rev. 2.00 Sep 20, 2005 page 483 of 800
R/W
EB3
3
0
R/W
EB2
2
0
REJ09B0260-0200
R/W
EB1
1
0
(Initial value)
EB0
R/W
0
0