HD64F3026X25 Renesas Electronics America, HD64F3026X25 Datasheet - Page 601

• Manufacturer Part Number: HD64F3026X25
• Description: MCU 3V 256K 100-TQFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8/300Hr

Specifications of HD64F3026X25

• Core Processor: H8/300H
• Core Size: 16-Bit
• Speed: 25MHz
• Connectivity: SCI, SmartCard
• Peripherals: PWM, WDT
• Number Of I /o: 70
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 100-TQFP, 100-VQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -

Notes: 1. Data transfer is performed by byte transfer. The lower 8 bits of the first address written to must be
Reprogram Data Computation Table
Original Data
(D)
2. Verify data is read in 16-bit (longword) units.
3. Reprogram data is determined by the operation shown in the table below (comparison between the data
4. A 128-byte area for storing program data, a 128-byte area for storing reprogram data, and a 128-byte area for storing additional data must be provided in RAM.
5. A write pulse of 30 s or 200 s is applied according to the progress of the programming operation. See Note 6 for details of the pulse widths.
7. The wait times and value of N are shown in section 21.2.6, Flash Memory Characteristics.
0
0
1
1
H'00 or H'80. A 128-byte data transfer must be performed even if writing fewer than 128 bytes;
in this case, H'FF data must be written to the extra addresses.
stored in the program data area and the verify data). Bits for which the reprogram data is 0 are programmed in the next reprogramming loop.
Therefore, even bits for which programming has been completed will be subjected to programming once again if the result of the subsequent verify operation is NG.
The contents of the reprogram data area and additional data area are modified as programming proceeds.
When writing of additional-programming data is executed, a 10 s write pulse should be applied. Reprogram data X' means reprogram data when the write pulse is applied.
Figure 18.11 Program/Program-Verify Flowchart (128-Byte Programming)
Verify Data
Note: Use a 10 s write pulse for additional programming.
Note 6: Write Pulse Width
(V)
Number of Writes n
0
1
0
1
Write pulse application subroutine
1000
998
999
10
11
12
13
Clear PSU bit in FLMCR1
Reprogram data storage
Additional-programming
1
2
3
4
5
6
7
8
9
Sub-Routine Write Pulse
Program data storage
Clear P bit in FLMCR1
Reprogram Data
Set PSU in FLMCR1
Set P bit in FLMCR1
data storage area
area (128 bytes)
area (128 bytes)
Wait (t
Wait (t
(128 bytes)
WDT enable
Wait (t
Wait (t
Disable WDT
RAM
End Sub
(X)
1
0
1
1
spsu
cpsu
Write Time (tsp) sec
sp
cp
) s
) s
) s
) s
200
200
200
200
200
200
200
200
200
200
30
30
30
30
30
30
Programming completed
Programming incomplete; reprogram
Still in erased state; no action
Comments
*
*
*
*
Start of programming
Programming halted
7
5
7
7
*
7
Increment address
Section 18 Flash Memory [H8/3024F-ZTAT Version]
Additional-Programming Data Computation Table
Reprogram Data
Successively write 128-byte data from additional-
programming data area in RAM to flash memory
NG
Transfer reprogram data to reprogram data area
(X')
Additional-programming data computation
0
0
1
1
Write Pulse (Additional programming)
Transfer additional-programming data to
Store 128-byte program data in program
data area consecutively to flash memory
Write 128-byte data in RAM reprogram
H'FF dummy write to verify address
data area and reprogram data area
additional-programming data area
Clear SWE bit in FLMCR1
Reprogram data computation
data verification completed?
Set SWE bit in FLMCR1
Clear PV bit in FLMCR1
Set PV bit in FLMCR1
Start of programming
End of programming
Verify Data
Rev. 2.00 Sep 20, 2005 page 561 of 800
Wait (t
Wait (t
Wait (t
Read verify data
Wait (t
Wait (t
Write data =
OK
OK
verify data?
Write pulse
OK
(V)
128-byte
START
0
1
0
1
6 n ?
m = 0?
m = 0
6 n?
n = 1
sswe
cswe
spvr
spv
cpv
OK
OK
Sub-Routine-Call
Sub-Routine-Call
) s
) s
) s
) s
) s
Programming Data (Y)
Additional-
NG
NG
NG
0
1
1
1
*
NG
*
*
*
*
*
7
See Note 6 for pulse width
7
7
2
3
7
*
*
*
4
1
4
*
*
m = 1
4
1
Perform programming in the erased state.
Do not perform additional programming
on previously programmed addresses.
Additional programming to be executed
Additional programming not to be executed
Additional programming not to be executed
Additional programming not to be executed
Clear SWE bit in FLMCR1
Programming failure
Wait (t
REJ09B0260-0200
n
cswe
N?
OK
Comments
) s
*
7
NG
n
n + 1
*
Reprogram
7