HD64F3026X25 Renesas Electronics America, HD64F3026X25 Datasheet - Page 91

• Manufacturer Part Number: HD64F3026X25
• Description: MCU 3V 256K 100-TQFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8/300Hr

Specifications of HD64F3026X25

• Core Processor: H8/300H
• Core Size: 16-Bit
• Speed: 25MHz
• Connectivity: SCI, SmartCard
• Peripherals: PWM, WDT
• Number Of I /o: 70
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 100-TQFP, 100-VQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -

2.8.4
Reset Exception Handling: Reset exception handling has the highest priority. The reset state is
entered when the
changes from low to high. When reset exception handling starts the CPU fetches a start address
from the exception vector table and starts program execution from that address. All interrupts,
including NMI, are disabled during the reset exception-handling sequence and immediately after it
ends.
Interrupt Exception Handling and Trap Instruction Exception Handling: When these
exception-handling sequences begin, the CPU references the stack pointer (ER7) and pushes the
program counter and condition code register on the stack. Next, if the UE bit in the system control
register (SYSCR) is set to 1, the CPU sets the I bit in the condition code register to 1. If the UE bit
Notes: 1.
RES = "High"
Exception-handling state
Exception Handling Operation
Bus-released state
2.
Reset state
From any state except hardware standby mode, a transition to the reset state occurs
whenever RES goes low.
From any state, a transition to hardware standby mode occurs when STBY goes low.
End of
exception
handling
R E S
End of bus
release
signal goes low. Reset exception handling starts after that, when
*1
Bus
request
Figure 2.13 State Transitions
STBY="High", RES ="Low"
Program execution state
NMI, IRQ , IRQ ,
or IRQ interrupt
Exception
Interrupt source
End of bus release
handling source
Bus request
2
0
1
Rev. 2.00 Sep 20, 2005 page 51 of 800
SLEEP instruction
with SSBY = 1
SLEEP
instruction
with SSBY = 0
Hardware standby mode
Software standby mode
Power-down state
Sleep mode
REJ09B0260-0200
Section 2 CPU
*2
R E S