HD64F3026X25 Renesas Electronics America, HD64F3026X25 Datasheet - Page 766

• Manufacturer Part Number: HD64F3026X25
• Description: MCU 3V 256K 100-TQFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8/300Hr

Specifications of HD64F3026X25

• Core Processor: H8/300H
• Core Size: 16-Bit
• Speed: 25MHz
• Connectivity: SCI, SmartCard
• Peripherals: PWM, WDT
• Number Of I /o: 70
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 100-TQFP, 100-VQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -

Appendix B Internal I/O Registers
8TCR0—Timer Control Register 0
8TCR1—Timer Control Register 1
Rev. 2.00 Sep 20, 2005 page 726 of 800
REJ09B0260-0200
Initial value
Read/Write
Bit
CMIEB
Compare match interrupt enable B
R/W
0
1
7
0
CMIB interrupt requested by CMFB is disabled
CMIB interrupt requested by CMFB is enabled
CMIEA
Compare match interrupt enable A
R/W
0
1
6
0
CMIA interrupt requested by CMFA is disabled
CMIA interrupt requested by CMFA is enabled
Timer overflow interrupt enable
OVIE
R/W
0
1
5
0
OVI interrupt requested by OVF is disabled
OVI interrupt requested by OVF is enabled
Counter clear 1 and 0
CCLR1
0
1
R/W
4
0
0
1
0
1
CCLR0
Note: * If the clock input of channel 0 is the 8TCNT1
R/W
Clock select 2 to 0
Clearing is disabled
Cleared by compare match A
Cleared by compare match B/input capture B
Cleared by input capture B
3
0
0
1
H'FFF80
H'FFF81
0
1
0
1
overflow signal and that of channel 1 is the
8TCNT0 compare match signal, no incrementing
clock is generated. Do not use this setting.
CKS2
R/W
2
0
0
1
0
1
0
1
0
1
Internal clock: counted on rising
edge of /8
Internal clock: counted on rising
edge of /64
Internal clock: counted on rising
edge of /8192
Channel 0:
Channel 1:
External clock: counted on falling edge
External clock: counted on rising edge
External clock: counted on both
rising and falling edges
Clock input is disabled
Count on 8TCNT1 overflow signal *
Count on 8TCNT0 compare match A *
CKS1
R/W
1
0
CKS0
R/W
0
0
8-bit timer channel 0
8-bit timer channel 1