HD64F3026X25 Renesas Electronics America, HD64F3026X25 Datasheet - Page 183

• Manufacturer Part Number: HD64F3026X25
• Description: MCU 3V 256K 100-TQFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8/300Hr

Specifications of HD64F3026X25

• Core Processor: H8/300H
• Core Size: 16-Bit
• Speed: 25MHz
• Connectivity: SCI, SmartCard
• Peripherals: PWM, WDT
• Number Of I /o: 70
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 100-TQFP, 100-VQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -

6.5
6.5.1
When the H8/3024 Group chip accesses external space, it can insert a 1-state idle cycle (T
between bus cycles in the following cases: when read accesses between different areas occur
consecutively, and when a write cycle occurs immediately after a read cycle. By inserting an idle
cycle it is possible, for example, to avoid data collisions between ROM, which has a long output
floating time, and high-speed memory, I/O interfaces, and so on.
The initial value of the ICIS1 and ICIS0 bits in BCR is 1, so that idle cycle insertion is performed
in the initial state. If there are no data collisions, the ICIS bits can be cleared.
Consecutive Reads between Different Areas: If consecutive reads between different areas occur
while the ICIS1 bit is set to 1 in BCR, an idle cycle is inserted at the start of the second read cycle.
Figure 6.17 shows an example of the operation in this case. In this example, bus cycle A is a read
cycle from ROM with a long output floating time, and bus cycle B is a read cycle from SRAM,
each being located in a different area. In (a), an idle cycle is not inserted, and a collision occurs in
bus cycle B between the read data from ROM and that from SRAM. In (b), an idle cycle is
inserted, and a data collision is prevented.
Address bus
Idle Cycle
Operation
Data bus
RD
Figure 6.17 Example of Idle Cycle Operation (ICIS1 = 1)
(a) Idle cycle not inserted
Bus cycle A Bus cycle B
T
1
Long buffer-off time
T
2
T
3
T
1
T
2
Data collision
Address bus
Data bus
Rev. 2.00 Sep 20, 2005 page 143 of 800
RD
Bus cycle A Bus cycle B
T
(b) Idle cycle inserted
1
T
2
Section 6 Bus Controller
T
3
T
REJ09B0260-0200
i
T
1
T
2
i
)