HD64F3026X25 Renesas Electronics America, HD64F3026X25 Datasheet - Page 280

• Manufacturer Part Number: HD64F3026X25
• Description: MCU 3V 256K 100-TQFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8/300Hr

Specifications of HD64F3026X25

• Core Processor: H8/300H
• Core Size: 16-Bit
• Speed: 25MHz
• Connectivity: SCI, SmartCard
• Peripherals: PWM, WDT
• Number Of I /o: 70
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 100-TQFP, 100-VQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -

Section 8 16-Bit Timer
1. Set bits TPSC2 to TPSC0 in 16TCR to select the counter clock source. If an external clock
2. For periodic counting, set CCLR1 and CCLR0 in 16TCR to have 16TCNT cleared at GRA
3. Set TIOR to select the output compare function of GRA or GRB, whichever was selected in
4. Write the count period in GRA or GRB, whichever was selected in step 2.
5. Set the STR bit to 1 in TSTR to start the timer counter.
Rev. 2.00 Sep 20, 2005 page 240 of 800
REJ09B0260-0200
source is selected, set bits CKEG1 and CKEG0 in 16TCR to select the desired edge(s) of the
external clock signal.
compare match or GRB compare match.
step 2.
Free-running and periodic counter operation
A reset leaves the counters (16TCNTs) in 16-bit timer channels 0 to 2 all set as free-running
counters. A free-running counter starts counting up when the corresponding bit in TSTR is set
to 1. When the count overflows from H'FFFF to H'0000, the OVF flag is set to 1 in TISRC.
After the overflow, the counter continues counting up from H'0000. Figure 8.13 illustrates
free-running counting.
When a channel is set to have its counter cleared by compare match, in that channel 16TCNT
operates as a periodic counter. Select the output compare function of GRA or GRB, set bit
CCLR1 or CCLR0 in 16TCR to have the counter cleared by compare match, and set the count
period in GRA or GRB. After these settings, the counter starts counting up as a periodic
counter when the corresponding bit is set to 1 in TSTR. When the count matches GRA or
GRB, the IMFA or IMFB flag is set to 1 in TISRA/TISRB and the counter is cleared to
H'0000. If the corresponding IMIEA or IMIEB bit is set to 1 in TISRA/TISRB, a CPU
interrupt is requested at this time. After the compare match, 16TCNT continues counting up
from H'0000. Figure 8.14 illustrates periodic counting.
H'FFFF
H'0000
STR0 to
STR2 bit
OVF
16TCNT value
Figure 8.13 Free-Running Counter Operation
Time