HD64F3026X25 Renesas Electronics America, HD64F3026X25 Datasheet - Page 259

• Manufacturer Part Number: HD64F3026X25
• Description: MCU 3V 256K 100-TQFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8/300Hr

Specifications of HD64F3026X25

• Core Processor: H8/300H
• Core Size: 16-Bit
• Speed: 25MHz
• Connectivity: SCI, SmartCard
• Peripherals: PWM, WDT
• Number Of I /o: 70
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 100-TQFP, 100-VQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -

Bit 0—PWM Mode 0 (PWM0): Selects whether channel 0 operates normally or in PWM mode.
Bit 0
PWM0
0
1
When bit PWM0 is set to 1 to select PWM mode, pin TIOCA
output goes to 1 at compare match with GRA0, and to 0 at compare match with GRB0.
8.2.4
TISRA is an 8-bit readable/writable register that indicates GRA compare match or input capture
and enables or disables GRA compare match and input capture interrupt requests.
TISRA is initialized to H'88 by a reset and in standby mode.
Bit 7—Reserved: This bit cannot be modified and is always read as 1.
Initial value
Read/Write
Note: * Only 0 can be written, to clear the flag.
Timer Interrupt Status Register A (TISRA)
Description
Channel 0 operates normally
Channel 0 operates in PWM mode
Bit
Reserved bit
—
—
7
1
IMIEA2
R/W
6
0
Input capture/compare match interrupt enable A2 to A0
These bits enable or disable interrupts by the IMFA flags
IMIEA1
R/W
5
0
IMIEA0
R/W
4
0
Reserved bit
—
—
3
1
Rev. 2.00 Sep 20, 2005 page 219 of 800
0
R/(W) *
becomes a PWM output pin. The
IMFA2
Input capture/compare match
flags A2 to A0
Status flags indicating GRA
compare match or input capture
2
0
R/(W) *
IMFA1
1
0
Section 8 16-Bit Timer
REJ09B0260-0200
R/(W) *
IMFA0
0
0
(Initial value)