HD64F3026X25 Renesas Electronics America, HD64F3026X25 Datasheet - Page 425

• Manufacturer Part Number: HD64F3026X25
• Description: MCU 3V 256K 100-TQFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8/300Hr

Specifications of HD64F3026X25

• Core Processor: H8/300H
• Core Size: 16-Bit
• Speed: 25MHz
• Connectivity: SCI, SmartCard
• Peripherals: PWM, WDT
• Number Of I /o: 70
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 100-TQFP, 100-VQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -

Section 12 Serial Communication Interface
Clock
An internal clock generated by the on-chip baud rate generator or an external clock input from the
SCK pin can be selected as the SCI transmit/receive clock. The clock source is selected by the
C/
bit in SMR and bits CKE1 and CKE0 in SCR. For details of SCI clock source selection, see
A
table 12.9.
When an external clock is input at the SCK pin, it must have a frequency 16 times the desired bit
rate.
When the SCI is operated on an internal clock, it can output a clock signal at the SCK pin. The
frequency of this output clock is equal to the bit rate. The phase is aligned as shown in figure 12.3
so that the rising edge of the clock occurs at the center of each transmit data bit.
0
D0
D1
D2
D3
D4
D5
D6
D7
0/1
1
1
1 frame
Figure 12.3 Phase Relationship between Output Clock and Serial Data
(Asynchronous Mode)
Transmitting and Receiving Data
SCI Initialization (Asynchronous Mode): Before transmitting or receiving data, clear the TE and
RE bits to 0 in SCR, then initialize the SCI as follows.
When changing the communication mode or format, always clear the TE and RE bits to 0 before
following the procedure given below. Clearing TE to 0 sets the TDRE flag to 1 and initializes
TSR. Clearing RE to 0, however, does not initialize the RDRF, PER, FER, and ORER flags, or
RDR, which retain their previous contents.
When an external clock is used the clock should not be stopped during initialization or subsequent
operation, since operation will be unreliable in this case.
Rev. 2.00 Sep 20, 2005 page 385 of 800
REJ09B0260-0200