HD64F3026X25 Renesas Electronics America, HD64F3026X25 Datasheet - Page 82

• Manufacturer Part Number: HD64F3026X25
• Description: MCU 3V 256K 100-TQFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8/300Hr

Specifications of HD64F3026X25

• Core Processor: H8/300H
• Core Size: 16-Bit
• Speed: 25MHz
• Connectivity: SCI, SmartCard
• Peripherals: PWM, WDT
• Number Of I /o: 70
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 100-TQFP, 100-VQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -

Section 2 CPU
Before Execution of BCLR Instruction
Execution of BCLR Instruction
BCLR #0, P4DDR ; Execute BCLR instruction on DDR
After Execution of BCLR Instruction
Explanation: To execute the BCLR instruction, the CPU begins by reading P4DDR. Since
P4DDR is a write-only register, it is read as H'FF, even though its true value is H'3F.
Next the CPU clears bit 0 of the read data, changing the value to H'FE.
Finally, the CPU writes this value (H'FE) back to P4DDR to complete the BCLR instruction.
As a result, P4
are set to 1, making P4
The BCLR instruction can be used to clear flags in the on-chip registers to 0. In the case of the
IRQ status register (ISR), for example, a flag must be read as a condition for clearing it, but when
using the BCLR instruction, if it is known that a flag has been set to 1 in an interrupt-handling
routine, for instance, it is not necessary to read the flag ahead of time.
Rev. 2.00 Sep 20, 2005 page 42 of 800
REJ09B0260-0200
Input/output
DDR
Input/output
DDR
0
DDR is cleared to 0, making P4
P4
Input
0
P4
Output
1
7
7
7
and P4
P4
Input
0
P4
Output
1
6
6
6
output pins.
P4
Output
1
P4
Output
1
5
5
P4
Output
1
P4
Output
1
0
an input pin. In addition, P4
4
4
P4
Output
1
P4
Output
1
3
3
P4
Output
1
P4
Output
1
2
2
7
P4
1
P4
1
DDR and P4
Output
Output
1
1
P4
Output
1
P4
Input
0
6
0
0
DDR