HD64F3026X25 Renesas Electronics America, HD64F3026X25 Datasheet - Page 402

MCU 3V 256K 100-TQFP

HD64F3026X25

Manufacturer Part Number
HD64F3026X25
Description
MCU 3V 256K 100-TQFP
Manufacturer
Renesas Electronics America
Series
H8® H8/300Hr
Datasheet

Specifications of HD64F3026X25

Core Processor
H8/300H
Core Size
16-Bit
Speed
25MHz
Connectivity
SCI, SmartCard
Peripherals
PWM, WDT
Number Of I /o
70
Program Memory Size
256KB (256K x 8)
Program Memory Type
FLASH
Ram Size
8K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Data Converters
A/D 8x10b; D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-20°C ~ 75°C
Package / Case
100-TQFP, 100-VQFP
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
HD64F3026X25
Manufacturer:
Renesas Electronics America
Quantity:
10 000
Section 12 Serial Communication Interface
The CPU can always read and write SCR. SCR is initialized to H'00 by a reset and in standby
mode.
Bit 7—Transmit Interrupt Enable (TIE): Enables or disables the transmit-data-empty interrupt
(TXI) requested when the TDRE flag in SSR is set to 1 due to transfer of serial transmit data from
TDR to TSR.
Bit 7
TIE
0
1
Note: * TXI interrupt requests can be cleared by reading the value 1 from the TDRE flag, then
Rev. 2.00 Sep 20, 2005 page 362 of 800
REJ09B0260-0200
Bit
Initial value
Read/Write
clearing it to 0; or by clearing the TIE bit to 0.
R/W
TIE
7
0
Description
Transmit-data-empty interrupt request (TXI) is disabled *
Transmit-data-empty interrupt request (TXI) is enabled
Transmit interrupt enable
Enables or disables transmit-data-empty interrupts (TxI)
R/W
RIE
6
0
Receive interrupt enable
Enables or disables receive-data-full interrupts (RxI) and
receive-error interrupts (ERI)
R/W
TE
5
0
Transmit enable
Enables or disables the transmitter
R/W
RE
4
0
Receive enable
Enables or disables the receiver
MPIE
R/W
3
0
Multiprocessor interrupt enable
Enables or disables multiprocessor
interrupts
TEIE
R/W
2
0
Transmit-end interrupt enable
Enables or disables transmit-end
interrupts (TEI)
CKE1
R/W
1
0
Clock enable 1/0
These bits select the
SCI clock source
CKE0
R/W
(Initial value)
0
0

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