HD64F3026X25 Renesas Electronics America, HD64F3026X25 Datasheet - Page 265

MCU 3V 256K 100-TQFP

HD64F3026X25

Manufacturer Part Number
HD64F3026X25
Description
MCU 3V 256K 100-TQFP
Manufacturer
Renesas Electronics America
Series
H8® H8/300Hr
Datasheet

Specifications of HD64F3026X25

Core Processor
H8/300H
Core Size
16-Bit
Speed
25MHz
Connectivity
SCI, SmartCard
Peripherals
PWM, WDT
Number Of I /o
70
Program Memory Size
256KB (256K x 8)
Program Memory Type
FLASH
Ram Size
8K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Data Converters
A/D 8x10b; D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-20°C ~ 75°C
Package / Case
100-TQFP, 100-VQFP
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
HD64F3026X25
Manufacturer:
Renesas Electronics America
Quantity:
10 000
8.2.6
TISRC is an 8-bit readable/writable register that indicates 16TCNT overflow or underflow and
enables or disables overflow interrupt requests.
TISRC is initialized to H'88 by a reset and in standby mode.
Bit 7—Reserved: This bit cannot be modified and is always read as 1.
Bit 6—Overflow Interrupt Enable 2 (OVIE2): Enables or disables the interrupt requested by the
OVF2 when OVF2 flag is set to 1.
Bit 6
OVIE2
0
1
Initial value
Read/Write
Note: * Only 0 can be written, to clear the flag.
Timer Interrupt Status Register C (TISRC)
Description
OVI2 interrupt requested by OVF2 flag is disabled
OVI2 interrupt requested by OVF2 flag is enabled
Bit
Reserved bit
7
1
OVIE2
R/W
6
0
Overflow interrupt enable 2 to 0
These bits enable or disable interrupts by the OVF flags
OVIE1
R/W
5
0
OVIE0
R/W
4
0
Reserved bit
Rev. 2.00 Sep 20, 2005 page 225 of 800
3
1
R/(W) *
OVF2
Overflow flags 2 to 0
Status flags indicating
interrupts by OVF flags
2
0
R/(W) *
OVF1
Section 8 16-Bit Timer
1
0
REJ09B0260-0200
R/(W) *
OVF0
(Initial value)
0
0

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