HD64F3026X25 Renesas Electronics America, HD64F3026X25 Datasheet - Page 451

• Manufacturer Part Number: HD64F3026X25
• Description: MCU 3V 256K 100-TQFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8/300Hr

Specifications of HD64F3026X25

• Core Processor: H8/300H
• Core Size: 16-Bit
• Speed: 25MHz
• Connectivity: SCI, SmartCard
• Peripherals: PWM, WDT
• Number Of I /o: 70
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 100-TQFP, 100-VQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -

The receive margin in asynchronous mode can therefore be expressed as shown in equation (1).
From equation (1), if F = 0 and D = 0.5, the receive margin is 46.875%, as given by equation (2).
When D = 0.5 and F = 0:
This is a theoretical value. A reasonable margin to allow in system designs is 20% to 30%.
Restrictions on Use of an External Clock Source:
Note: In operation with an external clock source, be sure that t >4 states.
When an external clock source is used for the serial clock, after updates TDR, allow an
inversion of at least five system clock ( ) cycles before input of the serial clock to start
transmitting. If the serial clock is input within four states of the TDR update, a malfunction
may occur. (See figure 12.22)
SCK
TDRE
M = (0.5 –
M: Receive margin (%)
N: Ratio of clock frequency to bit rate (N = 16)
D: Clock duty cycle (D = 0 to 1.0)
L: Frame length (L = 9 to 12)
F: Absolute deviation of clock frequency
M = (0.5 –
= 46.875%
t
Figure 12.22 Example of Synchronous Transmission
2
2N
1
1
D0
16
) – (L – 0.5) F –
)
100%
D1
D2
D – 0.5
N
D3
(1 + F)
Section 12 Serial Communication Interface
Rev. 2.00 Sep 20, 2005 page 411 of 800
D4
100%
D5
. . . . . . . . (1)
. . . . . . . . (2)
D6
REJ09B0260-0200
D7