HD64F3026X25 Renesas Electronics America, HD64F3026X25 Datasheet - Page 543

• Manufacturer Part Number: HD64F3026X25
• Description: MCU 3V 256K 100-TQFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8/300Hr

Specifications of HD64F3026X25

• Core Processor: H8/300H
• Core Size: 16-Bit
• Speed: 25MHz
• Connectivity: SCI, SmartCard
• Peripherals: PWM, WDT
• Number Of I /o: 70
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 100-TQFP, 100-VQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -

17.6.1
When writing data or programs to flash memory, the program/program-verify flowchart shown in
figure 17.10 should be followed. Performing programming operations according to this flowchart
will enable data or programs to be written to flash memory without subjecting the device to
voltage stress or sacrificing program data reliability. Programming should be carried out 128 bytes
at a time.
The wait times after bits are set or cleared in the flash memory control register 1 (FLMCR1) and
the maximum number of programming operations (N) are shown in table 21.19 in section 21.2.6,
Flash Memory Characteristics.
Following the elapse of (t
is written consecutively to the write addresses. The lower 8 bits of the first address written to must
be H'00 and H'80, 128 consecutive byte data transfers are performed. The program address and
program data are latched in the flash memory. A 128-byte data transfer must be performed even if
writing fewer than 128 bytes; in this case, H'FF data must be written to the extra addresses.
Next, the watchdog timer (WDT) is set to prevent overprogramming due to program runaway, etc.
Set a value greater than (t
entering program mode (program setup) is performed next by setting the PSU bit in FLMCR1.
The operating mode is then switched to program mode by setting the P bit in FLMCR1 after the
elapse of at least (t
programming time. Make a program setting so that the time for one programming operation is
within the range of (t
The wait time after P bit setting must be changed according to the degree of progress through the
programming operation. For details see “Notes on Program/Program-Verify Mode.”
17.6.2
In program-verify mode, the data written in program mode is read to check whether it has been
correctly written in the flash memory.
After the elapse of the given programming time, clear the P bit in FLMCR1, then wait for at least
(t
watchdog timer setting is also cleared. The operating mode is then switched to program-verify
mode by setting the PV bit in FLMCR1. Before reading in program-verify mode, a dummy write
of H'FF data should be made to the addresses to be read. The dummy write should be executed
after the elapse of (t
in 16-bit units), the data at the latched address is read. Wait at least (t
cp
) µs before clearing the PSU bit to exit program mode. After exiting program mode, the
Program Mode
Program-Verify Mode
spsu
spv
sp
) µs. The time during which the P bit is set is the flash memory
) µs or more. When the flash memory is read in this state (verify data is read
) µs.
spsu
sswe
) µs or more after the SWE bit is set to 1 in FLMCR1, 128-byte data
+ t
sp
+ t
cp
+ t
cpsu
) µs as the WDT overflow period. Preparation for
Section 17 Flash Memory [H8/3026F-ZTAT Version]
Rev. 2.00 Sep 20, 2005 page 503 of 800
spvr
) µs after the dummy write
REJ09B0260-0200