HD64F3026X25 Renesas Electronics America, HD64F3026X25 Datasheet - Page 553

• Manufacturer Part Number: HD64F3026X25
• Description: MCU 3V 256K 100-TQFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8/300Hr

Specifications of HD64F3026X25

• Core Processor: H8/300H
• Core Size: 16-Bit
• Speed: 25MHz
• Connectivity: SCI, SmartCard
• Peripherals: PWM, WDT
• Number Of I /o: 70
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 100-TQFP, 100-VQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -

17.7.3
In error protection, an error is detected when MCU runaway occurs during flash memory
programming/erasing *
algorithm, and the program/erase operation is aborted. Aborting the program/erase operation
prevents damage to the flash memory due to overprogramming or overerasing.
If the MCU malfunctions during flash memory programming/erasing, the FLER bit is set to 1 in
the flash memory status register (FLMSR2) and the error protection state is entered. FLMCR1,
FLMCR2, EBR1, and EBR2 settings *
the point at which the error occurred. Program mode or erase mode cannot be re-entered by re-
setting the P or E bit in FLMCR. However, PV and EV bit setting is enabled, and a transition can
be made to verify mode *
FLER bit setting conditions are as follows:
1. When flash memory is read during programming/erasing (including a vector read or instruction
2. Immediately after the start of exception handling during programming/erasing (excluding
3. When a SLEEP instruction (including software standby) is executed during
4. When the bus is released during programming/erasing
Notes: 1. State in which the P bit or E bit in FLMCR1 is set to 1. Note that NMI input is disabled
Figure 17.12 shows the flash memory state transition diagram.
fetch)
reset, illegal instruction, trap instruction, and division-by-zero exception handling)
programming/erasing
Error protection is released only by a
2. It is possible to perform a program-verify operation on the 128 bytes being
3. FLMCR1, EBR1, and EBR2 can be written to. However, the registers are initialized if
Error Protection
in this state.
programmed, or an erase-verify on the block being erased.
a transition is made to software standby mode while in the error protection state.
1
, or operation is not performed in accordance with the program/erase
2
.
3
are retained, but program mode or erase mode is aborted at
R E S
Section 17 Flash Memory [H8/3026F-ZTAT Version]
pin or WDT reset, or in hardware standby mode.
Rev. 2.00 Sep 20, 2005 page 513 of 800
REJ09B0260-0200