HD64F3026X25 Renesas Electronics America, HD64F3026X25 Datasheet - Page 431

• Manufacturer Part Number: HD64F3026X25
• Description: MCU 3V 256K 100-TQFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8/300Hr

Specifications of HD64F3026X25

• Core Processor: H8/300H
• Core Size: 16-Bit
• Speed: 25MHz
• Connectivity: SCI, SmartCard
• Peripherals: PWM, WDT
• Number Of I /o: 70
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 100-TQFP, 100-VQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -

In receiving, the SCI operates as follows:
Table 12.11 Receive Error Conditions
Receive Error Abbreviation
Overrun error
Framing error
Parity error
The SCI monitors the communication line. When it detects a start bit (0 bit), the SCI
synchronizes internally and starts receiving.
Receive data is stored in RSR in order from LSB to MSB.
The parity bit and stop bit are received.
After receiving these bits, the SCI carries out the following checks:
If these all checks pass, the RDRF flag is set to 1 and the received data is stored in RDR. If
one of the checks fails (receive error * ), the SCI operates as shown in table 12.11.
Note: * When a receive error occurs, further receiving is disabled. In receiving, the RDRF flag
When the RDRF flag is set to 1, if the RIE bit is set to 1 in SCR, a receive-data-full interrupt
(RXI) is requested. If the ORER, PER, or FER flag is set to 1 and the RIE bit in SCR is also
set to 1, a receive-error interrupt (ERI) is requested.
Parity check: The number of 1s in the receive data must match the even or odd parity
setting of in the O/
Stop bit check: The stop bit value must be 1. If there are two stop bits, only the first is
checked.
Status check: The RDRF flag must be 0, indicating that the receive data can be transferred
from RSR into RDR.
is not set to 1. Be sure to clear the error flags to 0.
ORER
FER
PER
E
bit in SMR.
Condition
Receiving of next data ends
while RDRF flag is still set to 1
in SSR
Stop bit is 0
Parity of received data differs
from even/odd parity setting in
SMR
Section 12 Serial Communication Interface
Rev. 2.00 Sep 20, 2005 page 391 of 800
Data Transfer
Receive data is not transferred
from RSR to RDR
Receive data is transferred
from RSR to RDR
Receive data is transferred
from RSR to RDR
REJ09B0260-0200