HD64F3026X25 Renesas Electronics America, HD64F3026X25 Datasheet - Page 17

• Manufacturer Part Number: HD64F3026X25
• Description: MCU 3V 256K 100-TQFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8/300Hr

Specifications of HD64F3026X25

• Core Processor: H8/300H
• Core Size: 16-Bit
• Speed: 25MHz
• Connectivity: SCI, SmartCard
• Peripherals: PWM, WDT
• Number Of I /o: 70
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 100-TQFP, 100-VQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -

Section 10 Programmable Timing Pattern Controller (TPC)
10.1 Overview........................................................................................................................... 311
10.2 Register Descriptions........................................................................................................ 315
10.3 Operation .......................................................................................................................... 328
10.4 Usage Notes ...................................................................................................................... 335
Section 11 Watchdog Timer
11.1 Overview........................................................................................................................... 337
11.2 Register Descriptions........................................................................................................ 339
9.7.7
9.7.8
9.7.9
10.1.1 Features................................................................................................................ 311
10.1.2 Block Diagram..................................................................................................... 312
10.1.3 Pin Configuration ................................................................................................ 313
10.1.4 Register Configuration......................................................................................... 314
10.2.1 Port A Data Direction Register (PADDR)........................................................... 315
10.2.2 Port A Data Register (PADR).............................................................................. 315
10.2.3 Port B Data Direction Register (PBDDR) ........................................................... 316
10.2.4 Port B Data Register (PBDR) .............................................................................. 316
10.2.5 Next Data Register A (NDRA) ............................................................................ 317
10.2.6 Next Data Register B (NDRB) ............................................................................ 319
10.2.7 Next Data Enable Register A (NDERA).............................................................. 321
10.2.8 Next Data Enable Register B (NDERB).............................................................. 322
10.2.9 TPC Output Control Register (TPCR)................................................................. 323
10.2.10 TPC Output Mode Register (TPMR)................................................................... 326
10.3.1 Overview.............................................................................................................. 328
10.3.2 Output Timing ..................................................................................................... 329
10.3.3 Normal TPC Output............................................................................................. 330
10.3.4 Non-Overlapping TPC Output............................................................................. 332
10.3.5 TPC Output Triggering by Input Capture............................................................ 334
10.4.1 Operation of TPC Output Pins............................................................................. 335
10.4.2 Note on Non-Overlapping Output ....................................................................... 335
11.1.1 Features................................................................................................................ 337
11.1.2 Block Diagram..................................................................................................... 338
11.1.3 Pin Configuration ................................................................................................ 338
11.1.4 Register Configuration......................................................................................... 339
11.2.1 Timer Counter (TCNT)........................................................................................ 339
11.2.2 Timer Control/Status Register (TCSR)................................................................ 340
Contention between 8TCNT Byte Write and Increment in 16-Bit Count Mode
(Cascaded Connection)........................................................................................ 306
Contention between Compare Matches A and B ................................................. 307
8TCNT Operation and Internal Clock Source Switchover .................................. 307
............................................................................................. 337
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