HD64F3026X25 Renesas Electronics America, HD64F3026X25 Datasheet - Page 35

• Manufacturer Part Number: HD64F3026X25
• Description: MCU 3V 256K 100-TQFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8/300Hr

Specifications of HD64F3026X25

• Core Processor: H8/300H
• Core Size: 16-Bit
• Speed: 25MHz
• Connectivity: SCI, SmartCard
• Peripherals: PWM, WDT
• Number Of I /o: 70
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 100-TQFP, 100-VQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -

Section 1 Overview
Table 1.1
Table 1.2
Table 1.3
Table 1.4
Section 2 CPU
Table 2.1
Table 2.2
Table 2.3
Table 2.4
Table 2.5
Table 2.6
Table 2.7
Table 2.8
Table 2.9
Table 2.10
Table 2.11
Table 2.12
Table 2.13
Table 2.14
Section 3 MCU Operating Modes
Table 3.1
Table 3.2
Table 3.3
Table 3.4
Section 4 Exception Handling
Table 4.1
Table 4.2
Section 5 Interrupt Controller
Table 5.1
Table 5.2
Table 5.3
Table 5.4
Table 5.5
Features................................................................................................................
Comparison of H8/3024 Group Pin Arrangements..............................................
Pin Functions ....................................................................................................... 10
Pin Assignments in Each Mode (FP-100B or TFP-100B, FP-100A) .................. 15
Instruction Classification ..................................................................................... 29
Instructions and Addressing Modes..................................................................... 30
Data Transfer Instructions ................................................................................... 32
Arithmetic Operation Instructions ....................................................................... 33
Logic Operation Instructions ............................................................................... 35
Shift Instructions.................................................................................................. 35
Bit Manipulation Instructions .............................................................................. 36
Branching Instructions......................................................................................... 38
System Control Instructions................................................................................. 39
Block Transfer Instruction ................................................................................... 40
Addressing Modes ............................................................................................... 43
Absolute Address Access Ranges........................................................................ 44
Effective Address Calculation ............................................................................. 46
Exception Handling Types and Priority............................................................... 50
Operating Mode Selection ................................................................................... 57
Registers .............................................................................................................. 58
Pin Functions in Each Mode................................................................................ 64
Address Maps in Mode 5..................................................................................... 65
Exception Types and Priority .............................................................................. 71
Exception Vector Table ....................................................................................... 73
Interrupt Pins ....................................................................................................... 85
Interrupt Controller Registers .............................................................................. 85
Interrupt Sources, Vector Addresses, and Priority............................................... 97
UE, I, and UI Bit Settings and Interrupt Handling............................................... 100
Interrupt Response Time...................................................................................... 106
Tables
Rev. 2.00 Sep 20, 2005 page xxxiii of xxxviii
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