HD64F3026X25 Renesas Electronics America, HD64F3026X25 Datasheet - Page 628

• Manufacturer Part Number: HD64F3026X25
• Description: MCU 3V 256K 100-TQFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8/300Hr

Specifications of HD64F3026X25

• Core Processor: H8/300H
• Core Size: 16-Bit
• Speed: 25MHz
• Connectivity: SCI, SmartCard
• Peripherals: PWM, WDT
• Number Of I /o: 70
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 100-TQFP, 100-VQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -

Section 19 Clock Pulse Generator
19.5
The frequency divider divides the duty-adjusted clock signal to generate the system clock ( ). The
frequency division ratio can be changed dynamically by modifying the value in DIVCR, as
described below. Power consumption in the chip is reduced in almost direct proportion to the
frequency division ratio. The system clock generated by the frequency divider can be output at the
19.5.1
Table 19.4 summarizes the frequency division register.
Table 19.4 Frequency Division Register
Note: * Lower 20 bits of the address in advanced mode.
19.5.2
DIVCR is an 8-bit readable/writable register that selects the division ratio of the frequency
divider.
DIVCR is initialized to H'FC by a reset and in hardware standby mode. It is not initialized in
software standby mode.
Bits 7 to 2—Reserved: These bits cannot be modified and are always read as 1.
Rev. 2.00 Sep 20, 2005 page 588 of 800
REJ09B0260-0200
Address *
H'EE01B
pin.
Bit
Initial value
Read/Write
Frequency Divider
Register Configuration
Division Control Register (DIVCR)
Name
Division control register
—
—
7
1
—
—
6
1
Reserved bits
—
—
5
1
Abbreviation
DIVCR
—
—
4
1
—
—
3
1
R/W
R/W
—
—
2
1
Divide bits 1 and 0
These bits select the
frequency division ratio
DIV1
R/W
Initial Value
H'FC
1
0
DIV0
R/W
0
0