HD64F3026X25 Renesas Electronics America, HD64F3026X25 Datasheet - Page 33

• Manufacturer Part Number: HD64F3026X25
• Description: MCU 3V 256K 100-TQFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8/300Hr

Specifications of HD64F3026X25

• Core Processor: H8/300H
• Core Size: 16-Bit
• Speed: 25MHz
• Connectivity: SCI, SmartCard
• Peripherals: PWM, WDT
• Number Of I /o: 70
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 100-TQFP, 100-VQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -

Figure 20.3
Section 21 Electrical Characteristics
Figure 21.1
Figure 21.2
Figure 21.3
Figure 21.4
Figure 21.5
Figure 21.6
Figure 21.7
Figure 21.8
Figure 21.9
Figure 21.10 Interrupt Input Timing ......................................................................................... 633
Figure 21.11 Basic Bus Cycle: Two-State Access .................................................................... 634
Figure 21.12 Basic Bus Cycle: Three-State Access .................................................................. 635
Figure 21.13 Basic Bus Cycle: Three-State Access with One Wait State................................. 636
Figure 21.14 Bus-Release Mode Timing .................................................................................. 636
Figure 21.15 TPC and I/O Port Input/Output Timing ............................................................... 637
Figure 21.16 Timer Input/Output Timing ................................................................................. 637
Figure 21.17 Timer External Clock Input Timing..................................................................... 638
Figure 21.18 SCI Input Clock Timing ...................................................................................... 638
Figure 21.19 SCI Input/Output Timing in Synchronous Mode................................................. 638
Appendix C I/O Port Block Diagrams
Figure C.1
Figure C.2
Figure C.3
Figure C.4
Figure C.5
Figure C.6 (a) Port 6 Block Diagram (Pin P6
Figure C.6 (b) Port 6 Block Diagram (Pin P6
Figure C.6 (c) Port 6 Block Diagram (Pin P6
Figure C.6 (d) Port 6 Block Diagram (Pins P6
Figure C.6 (e) Port 6 Block Diagram (Pin P6
Figure C.7 (a) Port 7 Block Diagram (Pins P7
Figure C.7 (b) Port 7 Block Diagram (Pins P7
Figure C.8 (a) Port 8 Block Diagram (Pin P8
Figure C.8 (b) Port 8 Block Diagram (Pins P8
Figure C.8 (c) Port 8 Block Diagram (Pin P8
Figure C.8 (d) Port 8 Block Diagram (Pin P8
Figure C.9 (a) Port 9 Block Diagram (Pin P9
Starting and Stopping of System Clock Output ................................................... 605
Darlington Pair Drive Circuit (Example)............................................................. 611
Sample LED Circuit ............................................................................................ 611
Output Load Circuit............................................................................................. 615
Darlington Pair Drive Circuit (Example)............................................................. 622
Sample LED Circuit ............................................................................................ 622
Output Load Circuit............................................................................................. 626
Oscillator Settling Timing.................................................................................... 631
Reset Input Timing .............................................................................................. 632
Reset Output Timing............................................................................................ 632
Port 1 Block Diagram........................................................................................ 754
Port 2 Block Diagram........................................................................................ 755
Port 3 Block Diagram........................................................................................ 756
Port 4 Block Diagram........................................................................................ 757
Port 5 Block Diagram........................................................................................ 758
0
1
2
7
0
3
4
0
) ........................................................................ 759
) ........................................................................ 760
) ........................................................................ 761
) ........................................................................ 763
) ........................................................................ 765
) ........................................................................ 767
) ........................................................................ 768
) ........................................................................ 769
3
0
6
1
to P6
to P7
and P7
and P8
6
5
Rev. 2.00 Sep 20, 2005 page xxxi of xxxviii
) ............................................................ 762
) ............................................................ 764
7
2
).......................................................... 764
).......................................................... 766