HD64F3026X25 Renesas Electronics America, HD64F3026X25 Datasheet - Page 625

• Manufacturer Part Number: HD64F3026X25
• Description: MCU 3V 256K 100-TQFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8/300Hr

Specifications of HD64F3026X25

• Core Processor: H8/300H
• Core Size: 16-Bit
• Speed: 25MHz
• Connectivity: SCI, SmartCard
• Peripherals: PWM, WDT
• Number Of I /o: 70
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 100-TQFP, 100-VQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -

19.2.2
Circuit Configuration: An external clock signal can be input as shown in the examples in figure
19.5. If the XTAL pin is left open, the stray capacitance should not exceed 10 pF. If the stray
capacitance at the XTAL pin exceeds 10 pF in configuration a, use the connection shown in
configuration b instead, and hold the external clock high in standby mode.
External Clock: The external clock frequency should be equal to the system clock frequency when
not divided by the on-chip frequency divider. Table 19.3 shows the clock timing, figure 19.6
shows the external clock input timing, and figure 19.7 shows the external clock output settling
delay timing. When the appropriate external clock is input via the EXTAL pin, its waveform is
corrected by the on-chip oscillator and duty adjustment circuit.
When the appropriate external clock is input via the EXTAL pin, its waveform is corrected by the
on-chip oscillator and duty adjustment circuit. The resulting stable clock is output to external
devices after the external clock settling time (t
must remain reset with the reset signal low during t
External Clock Input
EXTAL
XTAL
EXTAL
XTAL
Figure 19.5 External Clock Input (Examples)
b. Complementary clock input at XTAL pin
a. XTAL pin left open
DEXT
Open
) has passed after the clock input. The system
DEXT
, while the clock output is unstable.
Rev. 2.00 Sep 20, 2005 page 585 of 800
Section 19 Clock Pulse Generator
External clock input
External clock input
REJ09B0260-0200