HD64F3026X25 Renesas Electronics America, HD64F3026X25 Datasheet - Page 229

• Manufacturer Part Number: HD64F3026X25
• Description: MCU 3V 256K 100-TQFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8/300Hr

Specifications of HD64F3026X25

• Core Processor: H8/300H
• Core Size: 16-Bit
• Speed: 25MHz
• Connectivity: SCI, SmartCard
• Peripherals: PWM, WDT
• Number Of I /o: 70
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 100-TQFP, 100-VQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -

7.11.2
Table 7.18 summarizes the registers of port A.
Table 7.18 Port A Registers
Address *
H'EE009
H'FFFD9
Note: * Lower 20 bits of the address in advanced mode.
Port A Data Direction Register (PADDR): PADDR is an 8-bit write-only register that can select
input or output for each pin in port A. When pins are used for TPC output, the corresponding
PADDR bits must also be set.
The pin functions that can be selected for pins PA
modes 3 to 5. For the method of selecting the pin functions, see tables 7.19 and 7.20.
The pin functions that can be selected for pins PA
method of selecting the pin functions, see table 7.21.
When port A functions as an input/output port, a pin in port A becomes an output port if the
corresponding PADDR bit is set to 1, and an input port if this bit is cleared to 0. In modes 3 and 4,
PA
PADDR is a write-only register. Its value cannot be read. All bits return 1 when read.
Modes
3 and 4
Modes
1, 2, 5,
6 and 7
Bit
7
DDR is fixed at 1 and PA
Initial value
Read/Write
Initial value
Read/Write
Register Descriptions
Name
Port A data direction
register
Port A data register
PA DDR
7
—
W
7
1
0
PA DDR
7
functions as the A
6
W
W
6
0
0
PADDR
PADR
PA DDR
5
W
W
5
0
0
Port A data direction 7 to 0
These bits select input or output for port A pins
R/W
W
R/W
PA DDR
20
7
3
to PA
to PA
address output pin.
4
W
W
4
0
0
4
0
Modes 1, 2, 5, 6 and 7
H'00
H'00
Rev. 2.00 Sep 20, 2005 page 189 of 800
differ between modes 1, 2, 6, and 7, and
are the same in modes 1 to 7. For the
PA DDR
3
W
W
3
0
0
PA DDR
Initial Value
2
W
W
2
0
0
Section 7 I/O Ports
PA DDR
REJ09B0260-0200
1
W
W
1
0
0
Modes 3, 4
H'80
H'00
PA DDR
0
W
W
0
0
0