HD64F3026X25 Renesas Electronics America, HD64F3026X25 Datasheet - Page 152

MCU 3V 256K 100-TQFP

HD64F3026X25

Manufacturer Part Number
HD64F3026X25
Description
MCU 3V 256K 100-TQFP
Manufacturer
Renesas Electronics America
Series
H8® H8/300Hr
Datasheet

Specifications of HD64F3026X25

Core Processor
H8/300H
Core Size
16-Bit
Speed
25MHz
Connectivity
SCI, SmartCard
Peripherals
PWM, WDT
Number Of I /o
70
Program Memory Size
256KB (256K x 8)
Program Memory Type
FLASH
Ram Size
8K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Data Converters
A/D 8x10b; D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-20°C ~ 75°C
Package / Case
100-TQFP, 100-VQFP
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
HD64F3026X25
Manufacturer:
Renesas Electronics America
Quantity:
10 000
Section 6 Bus Controller
6.1.4
Table 6.2 summarizes the bus controller’s registers.
Table 6.2
Address *
H'EE020
H'EE021
H'EE022
H'EE023
H'EE013
H'EE01F
H'EE01E
H'EE024
Notes: 1. Lower 20 bits of the address in advanced mode.
6.2
6.2.1
ABWCR is an 8-bit readable/writable register that selects 8-bit or 16-bit access for each area.
Bit
When ABWCR contains H'FF (selecting 8-bit access for all areas), the chip operates in 8-bit bus
mode: the upper data bus (D
bit is cleared to 0 in ABWCR, the chip operates in 16-bit bus mode with a 16-bit data bus (D
D
mode. In modes 2 and 4, ABWCR is initialized to H'00 by a reset and in hardware standby mode.
It is not initialized in software standby mode.
Rev. 2.00 Sep 20, 2005 page 112 of 800
REJ09B0260-0200
Modes
1, 3, 5, 6,
and 7
Modes
2 and 4
0
). In modes 1, 3, 5, 6, and 7, ABWCR is initialized to H'FF by a reset and in hardware standby
2. In modes 2 and 4, the initial value is H'00.
3. In modes 3 and 4, the initial value is H'EE.
Register Configuration
Register Descriptions
Bus Width Control Register (ABWCR)
1
Initial value
Read/Write
Initial value
Read/Write
Bus Controller Registers
Name
Bus width control register
Access state control register
Wait control register H
Wait control register L
Bus release control register
Chip select control register
Address control register
Bus control register
ABW7
R/W
R/W
7
1
0
15
to D
ABW6
R/W
R/W
6
1
0
8
) is valid, and port 4 is an input/output port. When at least one
ABW5
R/W
R/W
5
1
0
ABW4
R/W
R/W
4
1
0
Abbreviation
ABWCR
ASTCR
WCRH
WCRL
BRCR
CSCR
ADRCR
BCR
ABW3
R/W
R/W
3
1
0
ABW2
R/W
R/W
2
1
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
ABW1
R/W
R/W
1
1
0
Initial Value
H'FF *
H'FF
H'FF
H'FF
H'FE *
H'0F
H'FF
H'C6
ABW0
2
3
R/W
R/W
15
0
1
0
to

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