HD64F3026X25 Renesas Electronics America, HD64F3026X25 Datasheet - Page 52

MCU 3V 256K 100-TQFP

HD64F3026X25

Manufacturer Part Number
HD64F3026X25
Description
MCU 3V 256K 100-TQFP
Manufacturer
Renesas Electronics America
Series
H8® H8/300Hr
Datasheet

Specifications of HD64F3026X25

Core Processor
H8/300H
Core Size
16-Bit
Speed
25MHz
Connectivity
SCI, SmartCard
Peripherals
PWM, WDT
Number Of I /o
70
Program Memory Size
256KB (256K x 8)
Program Memory Type
FLASH
Ram Size
8K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Data Converters
A/D 8x10b; D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-20°C ~ 75°C
Package / Case
100-TQFP, 100-VQFP
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
HD64F3026X25
Manufacturer:
Renesas Electronics America
Quantity:
10 000
Section 1 Overview
Rev. 2.00 Sep 20, 2005 page 12 of 800
REJ09B0260-0200
Type
Bus
control
16-bit
timer
8-bit timer TMO
Program-
mable
timing
pattern
controller
(TPC)
Serial
communi-
cation
interface
(SCI)
A/D
converter
Symbol
W A I T
TCLKD to
TCLKA
TIOCA
TIOCA
TIOCB
TIOCB
TMO
TMIO
TMIO
TCLKD to
TCLKA
TP
TP
TxD
TxD
RxD
RxD
SCK
SCK
AN
AN
A D T R G
15
0
7
0
1
0
1
0
to
1
0
,
0
2
to
,
,
1
3
,
,
2
0
2
0
to
to
9 to 2,
100 to 93
13, 12
15, 14
17, 16
85 to 78
90
FP-100B
TFP-100B FP-100A I/O
58
96 to 93
99, 97, 95 1, 99, 97 Input/
100, 98,
96
2, 4
3, 5
96 to 93
Pin No.
11 to 4,
2, 1,
100 to
95
15, 14
17, 16
19, 18
87 to 80 Input
92
60
98 to 95 Input
2, 100,
98
4, 6
5, 7
98 to 95 Input
Output TPC output 15 to 0: Pulse output
Output Transmit data (channels 0, 1): SCI data
Input
Input/
output
Input
Input
output
Input/
output
Output Compare match output: Compare match
Input/
output
output
Receive data (channels 0, 1): SCI data input
Serial clock (channels 0, 1): SCI clock
input/output
Analog 7 to 0: Analog input pins
A/D conversion external trigger input:
External trigger input for starting A/D
conversion
Name and Function
Wait: Requests insertion of wait states in bus
cycles during access to the external address
space
Clock input D to A: External clock inputs
Input capture/output compare A2 to A0:
GRA2 to GRA0 output compare or input
capture, or PWM output
Input capture/output compare B2 to B0:
GRB2 to GRB0 output compare or input
capture
output pins
Input capture input/compare match
output: Input capture input or compare match
output pins
Counter external clock input: These pins
input an external clock to the counters.

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