HD64F3026X25 Renesas Electronics America, HD64F3026X25 Datasheet - Page 218

• Manufacturer Part Number: HD64F3026X25
• Description: MCU 3V 256K 100-TQFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8/300Hr

Specifications of HD64F3026X25

• Core Processor: H8/300H
• Core Size: 16-Bit
• Speed: 25MHz
• Connectivity: SCI, SmartCard
• Peripherals: PWM, WDT
• Number Of I /o: 70
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 100-TQFP, 100-VQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -

Section 7 I/O Ports
Port 8 Data Direction Register (P8DDR): P8DDR is an 8-bit write-only register that can select
input or output for each pin in port 8.
Bits 7 to 5 are reserved. They are fixed at 1, and cannot be modified.
Bit
Modes
1 to 4
Modes
5 to 7
P8DDR is a write-only register. Its value cannot be read. All bits return 1 when read.
P8DDR is initialized to H'F0 in modes 1 to 4, and to H'E0 in modes 5 to 7, by a reset and in
hardware standby mode. In software standby mode P8DDR retains its previous setting. Therefore,
if a transition is made to software standby mode while port 8 is functioning as an input/output port
and a P8DDR bit is set to 1, the corresponding pin maintains its output state.
Rev. 2.00 Sep 20, 2005 page 178 of 800
REJ09B0260-0200
Modes 1 to 5 (Expanded Modes)
When bits in P8DDR bit are set to 1, P8
P8DDR are cleared to 0, the corresponding pins become input ports.
In modes 1 to 4 (expanded modes with on-chip ROM disabled), following a reset P8
as the
ROM enabled), following a reset
Modes 6 and 7 (Single-Chip Mode)
Port 8 is a generic input/output port. A pin in port 8 becomes an output port if the
corresponding P8DDR bit is set to 1, and an input port if this bit is cleared to 0.
Initial value
Read/Write
Initial value
Read/Write
C S
0
output, while
—
—
—
7
1
1
Reserved bits
C S
1
to
—
—
—
6
1
1
C S
C S
3
are input ports. In mode 5 (expanded mode with on-chip
0
to
—
—
—
5
1
1
4
C S
to P8
3
are all input ports.
P8 DDR
1
become
4
W
W
4
1
0
P8 DDR
Port 8 data direction 4 to 0
These bits select input or
output for port 8 pins
C S
3
W
W
0
3
0
0
to
C S
P8 DDR
3
output pins. When bits in
2
W
W
2
0
0
P8 DDR
1
W
W
1
0
0
4
P8 DDR
functions
0
W
W
0
0
0