HD64F3026X25 Renesas Electronics America, HD64F3026X25 Datasheet - Page 51

• Manufacturer Part Number: HD64F3026X25
• Description: MCU 3V 256K 100-TQFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8/300Hr

Specifications of HD64F3026X25

• Core Processor: H8/300H
• Core Size: 16-Bit
• Speed: 25MHz
• Connectivity: SCI, SmartCard
• Peripherals: PWM, WDT
• Number Of I /o: 70
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 100-TQFP, 100-VQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -

Type
System
control
Interrupts NMI
Address
bus
Data bus
Bus
control
Symbol
R E S
R E S O
FWE
S T B Y
B R E Q
B A C K
I R Q
I R Q
A
D
C S
C S
A S
R D
H W R
L W R
23
15
7
0
to A
to D
5
0
to
to
0
0
FP-100B
TFP-100B FP-100A I/O
63
10
10
62
59
60
17, 16,
90 to 87
97 to 100,
56 to 45,
43 to 36
34 to 23,
21 to 18
2 to 5,
88 to 91
69
70
71
72
64
Pin No.
65
12
12
64
61
62
19, 18,
92 to 89
99, 100,
1, 2,
58 to 47,
45 to 38
36 to 25,
23 to 20
4 to 7, 90
to 93
71
72
73
74
66
Input
Output Reset output (On-chip mask ROM
Input
Input
Input
Output Bus request acknowledge: Indicates that
Input
Input
Output Address bus: Outputs address signals
Input/
output
Output Chip select: Select signals for areas 7 to 0
Output Address strobe: Goes low to indicate valid
Output Read: Goes low to indicate reading from the
Output High write: Goes low to indicate writing to the
Output Low write: Goes low to indicate writing to the
Name and Function
Reset input: When driven low, this pin resets
the chip. This pin must be driven low at
power-up.
versions): Outputs the reset signal generated
by the watchdog timer to external devices
Write enable signal (On-chip flash memory
versions): Flash memory programming
control signal
Standby: When driven low, this pin forces
a transition to hardware standby mode
Bus request: Used by an external bus
master to request the bus right
the bus has been granted to an external bus
master
Nonmaskable interrupt: Requests a
nonmaskable interrupt
Interrupt request 5 to 0: Maskable interrupt
request pins
Data bus: Bidirectional data bus
address output on the address bus
external address space
external address space; indicates valid data
on the upper data bus (D
external address space; indicates valid data
on the lower data bus (D
Rev. 2.00 Sep 20, 2005 page 11 of 800
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15
Section 1 Overview
to D
REJ09B0260-0200
to D
0
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8
).