HD64F3026X25 Renesas Electronics America, HD64F3026X25 Datasheet - Page 558

• Manufacturer Part Number: HD64F3026X25
• Description: MCU 3V 256K 100-TQFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8/300Hr

Specifications of HD64F3026X25

• Core Processor: H8/300H
• Core Size: 16-Bit
• Speed: 25MHz
• Connectivity: SCI, SmartCard
• Peripherals: PWM, WDT
• Number Of I /o: 70
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 100-TQFP, 100-VQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -

Section 17 Flash Memory [H8/3026F-ZTAT Version]
17.9
All interrupts, including NMI input, should be disabled while flash memory is being programmed
or erased (while the P bit or E bit is set in FLMCR1), and while the boot program is executing in
boot mode *
1. NMI input during programming or erasing might cause a violation of the programming or
2. In the NMI exception handling sequence during programming or erasing, the vector would not
3. If NMI input occurred during boot program execution, it would not be possible to execute the
For these reasons, in on-board programming mode alone there are conditions for disabling NMI
input, as an exception to the general rule. However, this provision does not guarantee normal
erasing and programming or MCU operation. All interrupt requests (exception handling and bus
release), including NMI, must therefore be restricted inside and outside the MCU during FWE
application. NMI input is also disabled in the error protection state and while the P or E bit
remains set in FLMCR1 during flash memory emulation in RAM.
Notes: 1. This is the interval until a branch is made to the boot program area in the on-chip RAM
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REJ09B0260-0200
erasing algorithm, with the result that normal operation could not be assured.
be read correctly *
normal boot mode sequence.
2. The vector may not be read correctly in this case for the following two reasons:
NMI Input Disabling Conditions
(This branch takes place immediately after transfer of the user program is completed).
Consequently, after the branch to the RAM area, NMI input is enabled except during
programming and erasing. Interrupt requests must therefore be disabled inside and
outside the MCU until the user program has completed initial programming (including
the vector table and the NMI interrupt handling routine).
• If flash memory is read while being programmed or erased (while the P bit or E bit
• If the entry in the interrupt vector table has not been programmed yet, interrupt
1
, to give priority to the program or erase operation. There are three reasons for this:
is set in FLMCR1), correct read data will not be obtained (undetermined values will
be returned).
exception handling will not be executed correctly.
2
, possibly resulting in MCU runaway.