HD64F3026X25 Renesas Electronics America, HD64F3026X25 Datasheet - Page 409

• Manufacturer Part Number: HD64F3026X25
• Description: MCU 3V 256K 100-TQFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8/300Hr

Specifications of HD64F3026X25

• Core Processor: H8/300H
• Core Size: 16-Bit
• Speed: 25MHz
• Connectivity: SCI, SmartCard
• Peripherals: PWM, WDT
• Number Of I /o: 70
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 100-TQFP, 100-VQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -

Bit 4
FER
0
1
Notes: 1. Clearing the RE bit to 0 in SCR does not affect the FER flag, which retains its previous
Bit 4
ERS
0
1
Note: * Clearing the TE bit to 0 in SCR does not affect the ERS flag, which retains its previous
For serial communication interface (SMIF bit in SCMR cleared to 0)
Indicates that data reception ended abnormally due to a framing error in asynchronous mode.
For Smart Card Interface (SMIF Bit in SCMR Set to 1)
Indicates the status of the error signal sent back from the receiving side during transmission.
Framing errors are not detected in smart card interface mode.
value.
2. When the stop bit length is 2 bits, only the first bit is checked for a value of 1. The
value.
second stop bit is not checked. When a framing error occurs the SCI transfers the
receive data into RDR but does not set the RDRF flag. Serial receiving cannot continue
while the FER flag is set to 1. In synchronous mode, serial transmitting is also disabled.
Description
Receiving is in progress or has ended normally *
[Clearing conditions]
A receive framing error occurred
[Setting condition]
The stop bit at the end of the receive data is checked for a value of 1, and is
found to be 0. *
Description
Normal reception, no error signal *
[Clearing conditions]
An error signal has been sent from the receiving side indicating detection of a
parity error
[Setting condition]
The error signal is low when sampled
The chip is reset or enters standby mode
Read FER when FER = 1, then write 0 in FER
The chip is reset or enters standby mode
Read ERS when ERS = 1, then write 0 in ERS
2
Section 12 Serial Communication Interface
Rev. 2.00 Sep 20, 2005 page 369 of 800
1
REJ09B0260-0200
(Initial value)
(Initial value)