HD64F3026X25 Renesas Electronics America, HD64F3026X25 Datasheet - Page 169

• Manufacturer Part Number: HD64F3026X25
• Description: MCU 3V 256K 100-TQFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8/300Hr

Specifications of HD64F3026X25

• Core Processor: H8/300H
• Core Size: 16-Bit
• Speed: 25MHz
• Connectivity: SCI, SmartCard
• Peripherals: PWM, WDT
• Number Of I /o: 70
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 100-TQFP, 100-VQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -

6.3.4
For each of areas 0 to 7, the H8/3024 Group can output a chip select signal (
low when the corresponding area is selected in expanded mode. Figure 6.4 shows the output
timing of a
Output of
(DDR) of the corresponding port.
In the expanded modes with on-chip ROM disabled, a reset leaves pin
pins
DDR bits must be set to 1. In the expanded modes with on-chip ROM enabled, a reset leaves pins
C S
bits must be set to 1. For details, see section 7, I/O Ports.
Output of
register (CSCR). A reset leaves pins
C S
When the on-chip ROM, on-chip RAM, and internal I/O registers are accessed,
high. The
signals for SRAM and other devices.
0
4
to
to
C S
C S
C S
1
to
Chip Select Signals
3
7
C S
, the corresponding CSCR bits must be set to 1. For details, see section 7, I/O Ports.
C S
C S
C S
in the input state. To output chip select signals
C S
n
0
4
n signal.
3
signals are decoded from the address signals. They can be used as chip select
to
to
in the input state. To output chip select signals
C S
C S
Address bus
3
7
: Output of
: Output of
CS
Figure 6.4
n
C S
C S
C S
0
4
C S
to
to
n Signal Output Timing (n = 0 to 7)
4
C S
C S
to
3
7
C S
is enabled or disabled in the data direction register
is enabled or disabled in the chip select control
External address in area n
7
in the input state. To output chip select signals
Rev. 2.00 Sep 20, 2005 page 129 of 800
C S
0
to
C S
C S
1
to
3
, the corresponding DDR
C S
C S
Section 6 Bus Controller
0
3
, the corresponding
in the output state and
C S
0
C S
REJ09B0260-0200
to
0
C S
to
7
C S
) that goes
7
remain