HD64F3026X25 Renesas Electronics America, HD64F3026X25 Datasheet - Page 606
![MCU 3V 256K 100-TQFP](/photos/28/61/286123/100-tqfp__100-vqfp_sml.jpg)
HD64F3026X25
Manufacturer Part Number
HD64F3026X25
Description
MCU 3V 256K 100-TQFP
Manufacturer
Renesas Electronics America
Series
H8® H8/300Hr
Datasheet
1.DF3026XBL25V.pdf
(843 pages)
Specifications of HD64F3026X25
Core Processor
H8/300H
Core Size
16-Bit
Speed
25MHz
Connectivity
SCI, SmartCard
Peripherals
PWM, WDT
Number Of I /o
70
Program Memory Size
256KB (256K x 8)
Program Memory Type
FLASH
Ram Size
8K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Data Converters
A/D 8x10b; D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-20°C ~ 75°C
Package / Case
100-TQFP, 100-VQFP
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
HD64F3026X25
Manufacturer:
Renesas Electronics America
Quantity:
10 000
- Current page: 606 of 843
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Section 18 Flash Memory [H8/3024F-ZTAT Version]
18.7.2
Software protection can be implemented by setting the erase block register (EBR) and the RAMS
bit in the RAM control register (RAMCR). With software protection, setting the P or E bit in the
flash memory control register 1 (FLMCR1) does not cause a transition to program mode or erase
mode. (See table 18.9.)
Table 18.9 Software Protection
Item
Block
protection
Emulation
protection
Notes: 1. The RAM area overlapping flash memory can be written to.
Rev. 2.00 Sep 20, 2005 page 566 of 800
REJ09B0260-0200
2. It is possible to perform a program-verify operation on the 128 bytes being
3. All blocks are unerasable and block-by-block specification is not possible.
4. See section 4.2.2, Reset Sequence, and section 18.11, Flash Memory Programming
2. When not erasing, set EBR to H'00.
3. All blocks are unerasable and block-by-block specification is not possible.
Software Protection
programmed, or an erase-verify operation on the block being erased.
and Erasing Precautions. The H8/3024F-ZTAT version requires a minimum of 20
system clock cycles for a reset during operation.
Description
Erase protection can be set for individual
blocks by settings in erase block register
(EBR) *
is disabled.
Setting EBR to H'00 places all blocks in the
erase-protected state.
Setting the RAMS bit 1 in RAMCR places
all blocks in the program/erase-protected
state.
2
. However, programming protection
Program
—
Not
possible *
1
Functions
Erase
Not
possible
Not
possible *
3
Verify
Possible
Possible
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