HD64F3026X25 Renesas Electronics America, HD64F3026X25 Datasheet - Page 473

MCU 3V 256K 100-TQFP

HD64F3026X25

Manufacturer Part Number
HD64F3026X25
Description
MCU 3V 256K 100-TQFP
Manufacturer
Renesas Electronics America
Series
H8® H8/300Hr
Datasheet

Specifications of HD64F3026X25

Core Processor
H8/300H
Core Size
16-Bit
Speed
25MHz
Connectivity
SCI, SmartCard
Peripherals
PWM, WDT
Number Of I /o
70
Program Memory Size
256KB (256K x 8)
Program Memory Type
FLASH
Ram Size
8K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Data Converters
A/D 8x10b; D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-20°C ~ 75°C
Package / Case
100-TQFP, 100-VQFP
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
HD64F3026X25
Manufacturer:
Renesas Electronics America
Quantity:
10 000
Receiving Serial Data: Data reception in smart card mode uses the same processing procedure as
for the normal SCI. Figure 13.8 shows a sample reception processing flowchart.
1. Perform smart card interface mode initialization as described in Initialization above.
2. Check that the ORER flag and PER flag are cleared to 0 in SSR. If either is set, perform the
3. Repeat steps 2 and 3 until it can be confirmed that the RDRF flag is set to 1.
4. Read the receive data from RDR.
5. To continue receiving data, clear the RDRF flag to 0 and go back to step 2.
1. Data write
2. Transfer from TDR to TSR
3. Serial data output
Note: When the ERS flag is set, it should be cleared until transfer of the last bit (D7 in LSB-first
I/O data
TXI (TEND
interrupt)
appropriate receive error handling, then clear both the ORER and the PER flag to 0.
transmission, D0 in MSB-first transmission) of the retransmit data to be transmitted next has
been completed.
Figure 13.6 Relation Between Transmit Operation and Internal Registers
Ds
In case of normal transmission: TEND flag is set
In case of transmit error:
Da
Figure 13.7 Timing of TEND Flag Setting
Db
Dc
Data 1
Data 1
Data 1
TDR
Dd
De
12.5 etu
11.0 etu
Df
ERS flag is set
Steps 2 and 3 above are repeated until the
TEND flag is set.
(shift register)
Dg
Data 1
TSR
Rev. 2.00 Sep 20, 2005 page 433 of 800
Dh
Dp
Section 13 Smart Card Interface
Data remains in TDR
Data 1
Guard time
DE
REJ09B0260-0200
I/O signal
output
When GM = 0
When GM = 1

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