HD64F3026X25 Renesas Electronics America, HD64F3026X25 Datasheet - Page 767

• Manufacturer Part Number: HD64F3026X25
• Description: MCU 3V 256K 100-TQFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8/300Hr

Specifications of HD64F3026X25

• Core Processor: H8/300H
• Core Size: 16-Bit
• Speed: 25MHz
• Connectivity: SCI, SmartCard
• Peripherals: PWM, WDT
• Number Of I /o: 70
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 100-TQFP, 100-VQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -

8TCSR0—Timer Control/Status Register 0
Notes: 1. Only 0 can be written to bits 7 to 5 to clear these flags.
Compare match/input capture flag B
0
1
Initial value
Read/Write
2. TRGE is bit 7 of the A/D control register (ADCR).
[Clearing condition]
Read CMFB when CMFB = 1, then write 0 in CMFB.
[Setting conditions]
8TCNT = TCORB
• The 8TCNT value is transferred to TCORB by an input capture signal when TCORB functions as an input capture register.
Bit
R/(W) *
CMFB
7
0
Compare match flag A
1
0
1
R/(W) *
CMFA
[Clearing condition]
Read CMFA when CMFA = 1, then write 0 in CMFA.
[Setting condition]
8TCNT = TCORA
6
0
Timer overflow flag
1
0
1
R/(W) *
OVF
[Clearing condition]
Read OVF when OVF = 1, then write 0 in OVF.
[Setting condition]
8TCNT overflows from H'FF to H'00.
5
0
1
A/D trigger enable
TRGE *
0
1
ADTE
R/W
4
0
2
ADTE
Output/input capture edge select B3 and B2
Bit 4
8TCSR1
ICE in
0
1
0
1
OIS3
0
1
R/W
3
0
A/D converter start requests by compare match A or an external
trigger are disabled
A/D converter start requests by compare match A or an external
trigger are disabled
A/D converter start requests by an external trigger are enabled, and
A/D converter start requests by compare match A are disabled
A/D converter start requests by compare match A are enabled, and
A/D converter start requests by an external trigger are disabled
OIS3
Bit 3
Output select A1 and A0
0
1
0
1
Bit 1
OS1
H'FFF82
OIS2
0
1
R/W
2
0
OIS2
Bit 2
Bit 0
OS0
0
1
0
1
0
1
0
1
0
1
0
1
Rev. 2.00 Sep 20, 2005 page 727 of 800
No change at compare match A
0 output at compare match A
1 output at compare match A
No change at compare match B
0 output at compare match B
1 output at compare match B
Output toggles at compare match B
TCORB input capture on rising edge
TCORB input capture on falling edge
TCORB input capture on both rising
and falling edges
OS1
R/W
Output toggles at compare
match A
1
0
Description
Appendix B Internal I/O Registers
Description
Description
OS0
R/W
0
0
8-bit timer channel 0
REJ09B0260-0200