HD64F3026X25 Renesas Electronics America, HD64F3026X25 Datasheet - Page 382

• Manufacturer Part Number: HD64F3026X25
• Description: MCU 3V 256K 100-TQFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8/300Hr

Specifications of HD64F3026X25

• Core Processor: H8/300H
• Core Size: 16-Bit
• Speed: 25MHz
• Connectivity: SCI, SmartCard
• Peripherals: PWM, WDT
• Number Of I /o: 70
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 100-TQFP, 100-VQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -

Section 11 Watchdog Timer
Bits 2 to 0—Clock Select 2 to 0 (CKS2 to CKS0): These bits select one of eight internal clock
sources, obtained by prescaling the system clock ( ), for input to TCNT.
Bit 2
CKS2
0
1
11.2.3
RSTCSR is an 8-bit readable and writable register that indicates when a reset signal has been
generated by watchdog timer overflow, and controls external output of the reset signal.
Notes: The method for writing to RSTCSR is different from that for general registers to prevent
Bits 7 and 6 are initialized by input of a reset signal at the
reset signals generated by watchdog timer overflow.
Rev. 2.00 Sep 20, 2005 page 342 of 800
REJ09B0260-0200
Bit
Initial value
Read/Write
inadvertent overwriting. For details see section 11.2.4, Notes on Register Access.
*
Bit 1
CKS1
0
1
0
1
Reset Control/Status Register (RSTCSR)
Only 0 can be written in bit 7, to clear the flag.
Watchdog timer reset
Indicates that a reset signal has been generated
R/(W) *
WRST
Bit 0
CKS0
0
1
0
1
0
1
0
1
7
0
Reset output enable
Enables or disables external output of the reset signal
RSTOE
Description
R/W
/2
6
0
/32
/64
/128
/256
/512
/2048
/4096
—
—
5
1
—
—
4
1
R E S
Reserved bits
—
—
3
1
pin. They are not initialized by
—
—
2
1
—
—
1
1
(Initial value)
—
—
0
1