HD64F3026X25 Renesas Electronics America, HD64F3026X25 Datasheet - Page 230

• Manufacturer Part Number: HD64F3026X25
• Description: MCU 3V 256K 100-TQFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8/300Hr

Specifications of HD64F3026X25

• Core Processor: H8/300H
• Core Size: 16-Bit
• Speed: 25MHz
• Connectivity: SCI, SmartCard
• Peripherals: PWM, WDT
• Number Of I /o: 70
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 100-TQFP, 100-VQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -

Section 7 I/O Ports
PADDR is initialized to H'00 by a reset and in hardware standby mode in modes 1, 2, 5, 6, and 7.
It is initialized to H'80 by a reset and in hardware standby mode in modes 3 and 4. In software
standby mode it retains its previous setting. Therefore, if a transition is made to software standby
mode while port A is functioning as an input/output port and a PADDR bit is set to 1, the
corresponding pin maintains its output state.
Port A Data Register (PADR): PADR is an 8-bit readable/writable register that stores output
data for port A. When port A functions as an output port, the value of this register is output. When
a bit in PADDR is set to 1, if port A is read the value of the corresponding PADR bit is returned.
When a bit in PADDR is cleared to 0, if port A is read the corresponding pin logic level is read.
PADR is initialized to H'00 by a reset and in hardware standby mode. In software standby mode it
retains its previous setting.
Rev. 2.00 Sep 20, 2005 page 190 of 800
REJ09B0260-0200
Bit
Initial value
Read/Write
R/W
PA
0
7
7
R/W
PA
0
6
6
R/W
PA
0
5
5
Port A data 7 to 0
These bits store data for port A pins
R/W
PA
0
4
4
R/W
PA
0
3
3
R/W
PA
0
2
2
R/W
PA
0
1
1
R/W
PA
0
0
0