HD64F3026X25 Renesas Electronics America, HD64F3026X25 Datasheet - Page 758

• Manufacturer Part Number: HD64F3026X25
• Description: MCU 3V 256K 100-TQFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8/300Hr

Specifications of HD64F3026X25

• Core Processor: H8/300H
• Core Size: 16-Bit
• Speed: 25MHz
• Connectivity: SCI, SmartCard
• Peripherals: PWM, WDT
• Number Of I /o: 70
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 100-TQFP, 100-VQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -

Appendix B Internal I/O Registers
TISRB—Timer Interrupt Status Register B
Rev. 2.00 Sep 20, 2005 page 718 of 800
REJ09B0260-0200
Note: * Only 0 can be written to clear the flag.
Input capture/compare match interrupt enable B2
0
1
Input capture/compare match interrupt enable B1
IMIB2 interrupt requested by IMFB2 flag is disabled
IMIB2 interrupt requested by IMFB2 is enabled
0
1
Input capture/compare match interrupt enable B0
0
1
IMIB1 interrupt requested by IMFB1 flag is disabled
IMIB1 interrupt requested by IMFB1 is enabled
Read/Write:
Bit:
Initial value:
Input capture/compare match flag B2
IMIB0 interrupt requested by IMFB0 flag is disabled
IMIB0 interrupt requested by IMFB0 is enabled
0
1
Input capture/compare match flag B1
[Clearing condition]
Read IMFB2 when IMFB2=1, then write 0 in IMFB2.
[Setting conditions]
• 16TCNT2=GRB2 when GRB2 functions as an output compare register.
• 16TCNT2 value is transferred to GRB2 by an input capture signal when
0
1
GRB2 functions as an input capture register.
Input capture/compare match flag B0
0
1
[Clearing condition]
Read IMFB1 when IMFB1=1, then write 0 in IMFB1.
[Setting conditions]
• 16TCNT1=GRB1 when GRB1 functions as an output compare register.
• 16TCNT1 value is transferred to GRB1 by an input capture signal when
—
—
7
1
GRB1 functions as an input capture register.
[Clearing condition]
Read IMFB0 when IMFB0=1, then write 0 in IMFB0.
[Setting conditions]
• 16TCNT0=GRB0 when GRB0 functions as an output compare register.
• 16TCNT0 value is transferred to GRB0 by an input capture signal when GRB0
IMIEB2
functions as an input capture register.
R/W
6
0
IMIEB1
R/W
5
0
IMIEB0
R/W
4
0
H'FFF65
—
—
3
1
IMFB2
R/(W) *
(Initial value)
2
0
(Initial value)
IMFB1
R/(W) *
1
0
(Initial value)
16-bit timer (all channels)
IMFB0
R/(W) *
(Initial value)
0
0
(Initial value)
(Initial value)