HD64F3026X25 Renesas Electronics America, HD64F3026X25 Datasheet - Page 626

• Manufacturer Part Number: HD64F3026X25
• Description: MCU 3V 256K 100-TQFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8/300Hr

Specifications of HD64F3026X25

• Core Processor: H8/300H
• Core Size: 16-Bit
• Speed: 25MHz
• Connectivity: SCI, SmartCard
• Peripherals: PWM, WDT
• Number Of I /o: 70
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 100-TQFP, 100-VQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -

Section 19 Clock Pulse Generator
Table 19.3 (1)
Note: * t
Table 19.3 (2)
Note: * t
Rev. 2.00 Sep 20, 2005 page 586 of 800
REJ09B0260-0200
Item
External clock input low
pulse width
External clock input high
pulse width
External clock rise time
External clock fall time
Clock low pulse width
Clock high pulse width
External clock output
settling delay time
Item
External clock input low
pulse width
External clock input high
pulse width
External clock rise time
External clock fall time
Clock low pulse width
Clock high pulse width
External clock output
settling delay time
DEXT
DEXT
includes a
includes the
Clock Timing for On-Chip Flash Memory Versions
Clock Timing for On-Chip Mask ROM Versions
R E S
R E S
t
t
t
t
t
t
Symbol
t
t
t
t
Symbol
t
t
t
t
EXL
EXH
EXr
EXf
CL
CH
DEXT
EXL
EXH
EXr
EXf
CL
CH
DEXT
pulse width (t
pulse width (t
*
*
V
Min
t
55
t
55
—
—
0.4
80
0.4
80
500
V
Min
t
55
t
55
—
—
0.4
80
0.4
80
500
cyc
cyc
cyc
cyc
CC
CC
RESW
/ 2 - 5 —
/ 2 - 5 —
/ 2 - 5 —
/ 2 - 5 —
RESW
= 3.0 V to 3.6 V
= 3.0 V to 3.6 V
). t
). t
RESW
Max
Max
RESW
—
—
8
8
0.6
—
0.6
—
—
—
—
8
8
0.6
—
0.6
—
—
= 20 t
= 20 t
cyc
cyc
Unit
ns
ns
ns
ns
ns
ns
t
ns
t
ns
µs
Unit
ns
ns
ns
ns
ns
ns
t
ns
t
ns
µs
cyc
cyc
cyc
cyc
.
Test Conditions
Figure 19.7
Test Conditions
Figure 19.7
> 8 MHz
> 8 MHz
< 5 MHz
< 5 MHz
> 8 MHz
> 8 MHz
< 5 MHz
< 5 MHz
8 MHz
8 MHz
5 MHz
5 MHz
8 MHz
8 MHz
5 MHz
5 MHz
Figure 19.6
Figure 21.11
Figure 19.6
Figure 21.11