HD64F3026X25 Renesas Electronics America, HD64F3026X25 Datasheet - Page 435

• Manufacturer Part Number: HD64F3026X25
• Description: MCU 3V 256K 100-TQFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8/300Hr

Specifications of HD64F3026X25

• Core Processor: H8/300H
• Core Size: 16-Bit
• Speed: 25MHz
• Connectivity: SCI, SmartCard
• Peripherals: PWM, WDT
• Number Of I /o: 70
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 100-TQFP, 100-VQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -

In transmitting serial data, the SCI operates as follows:
Figure 12.11 shows an example of SCI transmit operation using a multiprocessor format.
Receiving Multiprocessor Serial Data: Figure 12.12 shows a sample flowchart for receiving
multiprocessor serial data and indicates the procedure to follow.
TDRE
TEND
The SCI monitors the TDRE flag in SSR. When the TDRE flag is cleared to 0, the SCI
recognizes that TDR contains new data, and loads this data from TDR into TSR.
After loading the data from TDR to TSR, the SCI sets the TDRE flag to 1 and starts
transmitting. If the TIE bit is set to 1 in SCR, the SCI requests a transmit-data-empty interrupt
(TXI) at this time.
Serial transmit data is transmitted in the following order from the TxD pin:
The SCI checks the TDRE flag when it outputs the stop bit. If the TDRE flag is 0, the SCI
loads new data from TDR into TSR, outputs the stop bit, then begins serial transmission of the
next frame. If the TDRE flag is 1, the SCI sets the TEND flag to 1 in SSR, outputs the stop
bit, then continues output of 1 bits in the mark state. If the TEIE bit is set to 1 in SCR, a
transmit-end interrupt (TEI) is requested at this time.
TXI interrupt
request
1
Start bit: One 0 bit is output.
Transmit data: 7 or 8 bits are output, LSB first.
Multiprocessor bit: One multiprocessor bit (MPBT value) is output.
Stop bit(s): One or two 1 bits (stop bits) are output.
Mark state: Output of 1 bits continues until the start bit of the next transmit data.
Start
bit
0
TXI interrupt handler
writes data in TDR and
clears TDRE flag to 0
D0
(8-Bit Data with Multiprocessor Bit and One Stop Bit)
Figure 12.11 Example of SCI Transmit Operation
D1
1 frame
Data
D7
processor
Multi-
TXI interrupt
request
0/1
bit
Stop
bit
1
Start
bit
0
Section 12 Serial Communication Interface
D0
Rev. 2.00 Sep 20, 2005 page 395 of 800
D1
Data
D7
processor
Multi-
bit
0/1
REJ09B0260-0200
TEI interrupt
request
Stop
bit
1
Idle (mark)
state