HD64F3026X25 Renesas Electronics America, HD64F3026X25 Datasheet - Page 428

• Manufacturer Part Number: HD64F3026X25
• Description: MCU 3V 256K 100-TQFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8/300Hr

Specifications of HD64F3026X25

• Core Processor: H8/300H
• Core Size: 16-Bit
• Speed: 25MHz
• Connectivity: SCI, SmartCard
• Peripherals: PWM, WDT
• Number Of I /o: 70
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 100-TQFP, 100-VQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -

Section 12 Serial Communication Interface
In transmitting serial data, the SCI operates as follows:
Figure 12.6 shows an example of SCI transmit operation in asynchronous mode.
Rev. 2.00 Sep 20, 2005 page 388 of 800
REJ09B0260-0200
TDRE
TEND
The SCI monitors the TDRE flag in SSR. When the TDRE flag is cleared to 0, the SCI
recognizes that TDR contains new data, and loads this data from TDR into TSR.
After loading the data from TDR to TSR, the SCI sets the TDRE flag to 1 and starts
transmitting. If the TIE bit is set to 1 in SCR, the SCI requests a transmit-data-empty interrupt
(TXI) at this time.
Serial transmit data is transmitted in the following order from the TxD pin:
The SCI checks the TDRE flag when it outputs the stop bit. If the TDRE flag is 0, the SCI
loads new data from TDR into TSR, outputs the stop bit, then begins serial transmission of the
next frame. If the TDRE flag is 1, the SCI sets the TEND flag to 1 in SSR, outputs the stop
bit, then continues output of 1 bits in the mark state. If the TEIE bit is set to 1 in SCR, a
transmit-end interrupt (TEI) is requested at this time.
TXI interrupt
request
1
Start bit: One 0 bit is output.
Transmit data: 7 or 8 bits are output, LSB first.
Parity bit or multiprocessor bit: One parity bit (even or odd parity),or one multiprocessor
bit is output. Formats in which neither a parity bit nor a multiprocessor bit is output can
also be selected.
Stop bit(s): One or two 1 bits (stop bits) are output.
Mark state: Output of 1 bits continues until the start bit of the next transmit data.
Figure 12.6 Example of SCI Transmit Operation in Asynchronous Mode
Start bit
0
TXI interrupt handler
writes data in TDR and
clears TDRE flag to 0
D0
D1
1 frame
(8-Bit Data with Parity and One Stop Bit)
Data
D7
Parity
bit
0/1
TXI interrupt
request
Stop
bit
1
Start
bit
0
D0
D1
Data
D7
Parity
bit
0/1
TEI interrupt
request
Stop
bit
1
Idle state
(mark state)
1