HD64F3026X25 Renesas Electronics America, HD64F3026X25 Datasheet - Page 557

• Manufacturer Part Number: HD64F3026X25
• Description: MCU 3V 256K 100-TQFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8/300Hr

Specifications of HD64F3026X25

• Core Processor: H8/300H
• Core Size: 16-Bit
• Speed: 25MHz
• Connectivity: SCI, SmartCard
• Peripherals: PWM, WDT
• Number Of I /o: 70
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 100-TQFP, 100-VQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -

Example of Flash Memory Block Area EB0 Overlapping
1. Set bits RAMS and RAM2 to RAM0 in RAMCR to 1,0, 0, 0, to overlap part of RAM onto the
2. Realtime programming is performed using the overlapping RAM.
3. After the program data has been confirmed, the RAMS bit is cleared, releasing RAM overlap.
4. The data written in the overlapping RAM is written into the flash memory space (EB0).
Notes: 1. When the RAMS bit is set to 1, program/erase protection is enabled for all blocks
area (EB0) for which realtime programming is required.
2. A RAM area cannot be erased by execution of software in accordance with the erase
3. Block area EB0 contains the vector table. When performing RAM emulation, the
4. As in on-board programming mode, care is required when applying and releasing FWE
5. When the emulation function is used, NMI input is prohibited when the P bit or E bit is
regardless of the value of RAM2 to RAM0 (emulation protection). In this state, setting
the P or E bit in FLMCR1 will not cause a transition to program mode or erase mode.
When actually programming or erasing a flash memory area, the RAMS bit should be
cleared to 0.
algorithm while flash memory emulation in RAM is being used.
vector table is needed in the overlap RAM.
to prevent erroneous programming or erasing. To prevent erroneous programming and
erasing due to program runaway during FWE application, in particular, the watchdog
timer should be set when the PSU, P, ESU, or E bit is set to 1 in FLMCR1, even while
the emulation function is being used.
set to 1 in FLMCR1, in the same way as with normal programming and erasing.
The P and E bits are cleared by a reset (including a watchdog timer reset), in standby
mode, when a high level is not being input to the FWE pin, or when the SWE bit in
FLMCR1 is 0 while a high level is being input to the FWE pin.
Section 17 Flash Memory [H8/3026F-ZTAT Version]
Rev. 2.00 Sep 20, 2005 page 517 of 800
REJ09B0260-0200