HD64F3026X25 Renesas Electronics America, HD64F3026X25 Datasheet - Page 461

MCU 3V 256K 100-TQFP

HD64F3026X25

Manufacturer Part Number
HD64F3026X25
Description
MCU 3V 256K 100-TQFP
Manufacturer
Renesas Electronics America
Series
H8® H8/300Hr
Datasheet

Specifications of HD64F3026X25

Core Processor
H8/300H
Core Size
16-Bit
Speed
25MHz
Connectivity
SCI, SmartCard
Peripherals
PWM, WDT
Number Of I /o
70
Program Memory Size
256KB (256K x 8)
Program Memory Type
FLASH
Ram Size
8K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Data Converters
A/D 8x10b; D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-20°C ~ 75°C
Package / Case
100-TQFP, 100-VQFP
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
HD64F3026X25
Manufacturer:
Renesas Electronics America
Quantity:
10 000
Bits 3 to 0: These bits operate as in normal serial communication. For details see section 12.2.7,
Serial Status Register (SSR). The setting conditions for transmit end (TEND), however, are
modified as follows.
Bit 2
TEND
0
1
Note: An etu (elementary time unit) is the time needed to transmit one bit.
13.2.3
The function of SMR bit 7 is modified in smart card interface mode. This change also causes a
modification to the function of bits 1 and 0 in the serial control register (SCR).
Bit 7—GSM Mode (GM): With the normal smart card interface, this bit is cleared to 0. Setting
this bit to 1 selects GSM mode, an additional mode for controlling the timing for setting the
TEND flag that indicates completion of transmission, and the type of clock output used. The
details of the additional clock output control mode are specified by the CKE1 and CKE0 bits in
the serial control register (SCR).
Bit
Initial value
Read/Write
Serial Mode Register (SMR)
Description
Transmission is in progress
[Clearing condition]
Software reads TDRE while it is set to 1, then writes 0 in the TDRE flag.
End of transmission
[Setting conditions]
The chip is reset or enters standby mode.
The TE bit and FER/ERS bit are both cleared to 0 in SCR.
TDRE is 1 and FER/ERS is 0 at a time 2.5 etu after the last bit of a 1-byte serial
character is transmitted (normal transmission).
R/W
GM
7
0
CHR
R/W
6
0
R/W
PE
5
0
R/W
O/E
4
0
Rev. 2.00 Sep 20, 2005 page 421 of 800
STOP
R/W
3
0
Section 13 Smart Card Interface
R/W
MP
2
0
CKS1
R/W
REJ09B0260-0200
1
0
(Initial value)
CKS0
R/W
0
0

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