HD64F3026X25 Renesas Electronics America, HD64F3026X25 Datasheet - Page 590

• Manufacturer Part Number: HD64F3026X25
• Description: MCU 3V 256K 100-TQFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8/300Hr

Specifications of HD64F3026X25

• Core Processor: H8/300H
• Core Size: 16-Bit
• Speed: 25MHz
• Connectivity: SCI, SmartCard
• Peripherals: PWM, WDT
• Number Of I /o: 70
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 100-TQFP, 100-VQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -

Section 18 Flash Memory [H8/3024F-ZTAT Version]
Automatic SCI Bit Rate Adjustment:
When boot mode is initiated, the H8/3024F-ZTAT version measures the low period of the
asynchronous SCI communication data (H'00) transmitted continuously from the host. The SCI
transmit/receive format should be set as 8-bit data, 1 stop bit, no parity. The H8/3024F-ZTAT
version calculates the bit rate of the transmission from the host from the measured low period, and
transmits one H'00 byte to the host to indicate the end of bit rate adjustment. The host should
confirm that this adjustment end indication (H'00) has been received normally, and transmit one
H'55 byte to the H8/3024F-ZTAT version. If reception cannot be performed normally, initiate boot
mode again (reset), and repeat the above operations. Depending on the host’s transmission bit rate
and the H8/3024F-ZTAT version’s system clock frequency, there will be a discrepancy between
the bit rates of the host and the H8/3024F-ZTAT version. To ensure correct SCI operation, the
host’s transfer bit rate should be set to 4800, 9600, or 19,200 bps * .
Table 18.7 shows typical host transfer bit rates and system clock frequencies for which automatic
adjustment of the H8/3024F-ZTAT version bit rate is possible. The boot program should be
executed within this system clock range.
Table 18.7 System Clock Frequencies for which Automatic Adjustment of H8/3024F-ZTAT
Host Bit Rate (bps)
19,200
9,600
4,800
Note: * Only use a setting of 4800, 9600, or 19200 for the host’s bit rate. No other settings can be
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REJ09B0260-0200
used.
Although the H8/3024F-ZTAT version may also perform automatic bit rate adjustment
with bit rate and system clock combinations other than those shown in table 18.7, a degree
of error will arise between the bit rates of the host and the MCU, and subsequent transfer
will not be performed normally. Therefore, only a combination of bit rate and system
clock frequency within one of the ranges shown in table 18.7 can be used for boot mode
execution.
Version Bit Rate is Possible
Start
bit
D0
Low period (9 bits) measured (H'00 data)
System Clock Frequency for which Automatic Adjustment of
H8/3024F-ZTAT Version Bit Rate is Possible (MHz)
16 to 25
8 to 25
4 to 25
D1
D2
D3
D4
D5
D6
D7
(1 or more bits)
High period
Stop
bit