HD64F3026X25 Renesas Electronics America, HD64F3026X25 Datasheet - Page 13

• Manufacturer Part Number: HD64F3026X25
• Description: MCU 3V 256K 100-TQFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8/300Hr

Specifications of HD64F3026X25

• Core Processor: H8/300H
• Core Size: 16-Bit
• Speed: 25MHz
• Connectivity: SCI, SmartCard
• Peripherals: PWM, WDT
• Number Of I /o: 70
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 100-TQFP, 100-VQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -

Section 5 Interrupt Controller
5.1
5.2
5.3
5.4
5.5
Section 6 Bus Controller
6.1
6.2
6.3
Overview........................................................................................................................... 83
5.1.1
5.1.2
5.1.3
5.1.4
Register Descriptions........................................................................................................ 85
5.2.1
5.2.2
5.2.3
5.2.4
5.2.5
Interrupt Sources............................................................................................................... 95
5.3.1
5.3.2
5.3.3
Interrupt Operation ........................................................................................................... 100
5.4.1
5.4.2
5.4.3
Usage Notes ...................................................................................................................... 107
5.5.1
5.5.2
5.5.3
Overview........................................................................................................................... 109
6.1.1
6.1.2
6.1.3
6.1.4
Register Descriptions........................................................................................................ 112
6.2.1
6.2.2
6.2.3
6.2.4
6.2.5
6.2.6
6.2.7
Operation .......................................................................................................................... 124
6.3.1
Bus Release Control Register (BRCR) ................................................................ 118
Bus Control Register (BCR) ................................................................................ 120
Address Control Register (ADRCR) ................................................................... 123
Features................................................................................................................ 83
Block Diagram..................................................................................................... 84
Pin Configuration ................................................................................................ 85
Register Configuration......................................................................................... 85
System Control Register (SYSCR)...................................................................... 85
Interrupt Priority Registers A and B (IPRA, IPRB)............................................. 86
IRQ Status Register (ISR).................................................................................... 92
IRQ Enable Register (IER) .................................................................................. 93
IRQ Sense Control Register (ISCR) .................................................................... 94
External Interrupts ............................................................................................... 95
Internal Interrupts ................................................................................................ 96
Interrupt Exception Handling Vector Table......................................................... 96
Interrupt Handling Process .................................................................................. 100
Interrupt Exception Handling Sequence .............................................................. 105
Interrupt Response Time...................................................................................... 106
Contention between Interrupt and Interrupt-Disabling Instruction...................... 107
Instructions that Inhibit Interrupts ....................................................................... 108
Interrupts during EEPMOV Instruction Execution.............................................. 108
Features................................................................................................................ 109
Block Diagram..................................................................................................... 110
Pin Configuration ................................................................................................ 111
Register Configuration......................................................................................... 112
Bus Width Control Register (ABWCR)............................................................... 112
Access State Control Register (ASTCR) ............................................................. 113
Wait Control Registers H and L (WCRH, WCRL).............................................. 114
Chip Select Control Register (CSCR).................................................................. 122
Area Division....................................................................................................... 124
................................................................................................... 109
.......................................................................................... 83
Rev. 2.00 Sep 20, 2005 page xi of xxxviii