HD64F3026X25 Renesas Electronics America, HD64F3026X25 Datasheet - Page 400

• Manufacturer Part Number: HD64F3026X25
• Description: MCU 3V 256K 100-TQFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8/300Hr

Specifications of HD64F3026X25

• Core Processor: H8/300H
• Core Size: 16-Bit
• Speed: 25MHz
• Connectivity: SCI, SmartCard
• Peripherals: PWM, WDT
• Number Of I /o: 70
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 100-TQFP, 100-VQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -

Section 12 Serial Communication Interface
Bit 4—Parity Mode (O/
and checking. The O/
addition and checking, in asynchronous mode. The O/
mode, or when parity addition and checking is disabled in asynchronous mode.
Bit 4
O/
0
1
Notes: 1. When even parity is selected, the parity bit added to transmit data makes an even
Bit 3—Stop Bit Length (STOP): Selects one or two stop bits in asynchronous mode. This setting
is used only in asynchronous mode. In synchronous mod no stop bit is added, so the STOP bit
setting is ignored.
Bit 3
STOP
0
1
Notes: 1. One stop bit (with value 1) is added to the end of each transmitted character.
In receiving, only the first stop bit is checked, regardless of the STOP bit setting. If the second
stop bit is 1, it is treated as a stop bit. If the second stop bit is 0, it is treated as the start bit of the
next incoming character.
Rev. 2.00 Sep 20, 2005 page 360 of 800
REJ09B0260-0200
E
2. When odd parity is selected, the parity bit added to transmit data makes an odd number
2. Two stop bits (with value 1) are added to the end of each transmitted character.
number of 1s in the transmitted character and parity bit combined. Receive data must
have an even number of 1s in the received character and parity bit combined.
of 1s in the transmitted character and parity bit combined. Receive data must have an
odd number of 1s in the received character and parity bit combined.
Description
Even parity *
Odd parity *
Description
1 stop bit *
2 stop bits *
E
bit setting is only valid when the PE bit is set to 1, enabling parity bit
E
) : Specifies whether even parity or odd parity is used for parity addition
1
2
2
1
E
bit setting is ignored in synchronous
(Initial value)
(Initial value)