HD64F3026X25 Renesas Electronics America, HD64F3026X25 Datasheet - Page 639

• Manufacturer Part Number: HD64F3026X25
• Description: MCU 3V 256K 100-TQFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8/300Hr

Specifications of HD64F3026X25

• Core Processor: H8/300H
• Core Size: 16-Bit
• Speed: 25MHz
• Connectivity: SCI, SmartCard
• Peripherals: PWM, WDT
• Number Of I /o: 70
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 100-TQFP, 100-VQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -

Clear the BRLE bit in BRCR (inhibiting bus release) before making a transition to software
standby mode.
20.4.2
Software standby mode can be exited by input of an external interrupt at the NMI,
I R Q
Exit by Interrupt: When an NMI, IRQ
clock oscillator begins operating. After the oscillator settling time selected by bits STS2 to STS0
in SYSCR, stable clock signals are supplied to the entire chip, software standby mode ends, and
interrupt exception handling begins. Software standby mode is not exited if the interrupt enable
bits of interrupts IRQ
CPU.
Exit by
supplied immediately to the entire chip. The
clock oscillator to stabilize. When
Exit by
20.4.3
Bits STS2 to STS0 in SYSCR and bits DIV1 and DIV0 in DIVCR should be set as follows.
Crystal Resonator: Set STS2 to STS0, DIV1, and DIV0 so that the waiting time (for the clock to
stabilize) is at least 7 ms. Table 20.3 indicates the waiting times that are selected by STS2 to
STS0, DIV1, and DIV0 settings at various system clock frequencies.
When Using an External Clock: Set bits STS2 to STS0 and bits DIV0 and DIV1 to give a wait
time of at least 100 µs.
2
pin, or by input at the
R E S
S T B Y
Exit from Software Standby Mode
Selection of Waiting Time for Exit from Software Standby Mode
Input: When the
Input: Low input at the
0
, IRQ
1
R E S
, and IRQ
R E S
or
R E S
S T B Y
input goes low, the clock oscillator starts and clock pulses are
2
are cleared to 0, or if these interrupts are masked in the
S T B Y
0
goes high, the CPU starts reset exception handling.
, IRQ
pin.
R E S
1
pin causes a transition to hardware standby mode.
, or IRQ
signal must be held low long enough for the
2
interrupt request signal is received, the
Rev. 2.00 Sep 20, 2005 page 599 of 800
Section 20 Power-Down State
REJ09B0260-0200
I R Q
0
,
I R Q
1
, or