HD64F3026X25 Renesas Electronics America, HD64F3026X25 Datasheet - Page 59

• Manufacturer Part Number: HD64F3026X25
• Description: MCU 3V 256K 100-TQFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8/300Hr

Specifications of HD64F3026X25

• Core Processor: H8/300H
• Core Size: 16-Bit
• Speed: 25MHz
• Connectivity: SCI, SmartCard
• Peripherals: PWM, WDT
• Number Of I /o: 70
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 100-TQFP, 100-VQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -

2.1
The H8/300H CPU is a high-speed central processing unit with an internal 32-bit architecture that
is upward-compatible with the H8/300 CPU. The H8/300H CPU has sixteen 16-bit general
registers, can address a 16-Mbyte linear address space, and is ideal for realtime control.
2.1.1
The H8/300H CPU has the following features.
Upward compatibility with H8/300 CPU
Can execute H8/300 Series object programs
General-register architecture
Sixteen 16-bit general registers (also usable as sixteen 8-bit registers or eight 32-bit registers)
64 basic instructions
Eight addressing modes
16-Mbyte linear address space
High-speed operation
8/16/32-bit arithmetic and logic instructions
Multiply and divide instructions
Powerful bit-manipulation instructions
Register direct [Rn]
Register indirect [@ERn]
Register indirect with displacement [@(d:16, ERn) or @(d:24, ERn)]
Register indirect with post-increment or pre-decrement [@ERn+ or @–ERn]
Absolute address [@aa:8, @aa:16, or @aa:24]
Immediate [#xx:8, #xx:16, or #xx:32]
Program-counter relative [@(d:8, PC) or @(d:16, PC)]
Memory indirect [@@aa:8]
All frequently-used instructions execute in two to four states
Maximum clock frequency:
8/16/32-bit register-register add/subtract: 80 ns@25 MHz
8
16 ÷ 8-bit register-register divide:
Overview
Features
8-bit register-register multiply:
Section 2 CPU
25 MHz
560 ns@25 MHz
560 ns@25 MHz
Rev. 2.00 Sep 20, 2005 page 19 of 800
REJ09B0260-0200
Section 2 CPU